From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by mx.groups.io with SMTP id smtpd.web10.9179.1645703293746018472 for ; Thu, 24 Feb 2022 03:48:13 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=wuF1+J0R; spf=pass (domain: quicinc.com, ip: 199.106.114.39, mailfrom: quic_tpilar@quicinc.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1645703293; x=1677239293; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=+k1BsSmPWCgyAUH4mVX69yrSbHTrYnT5EPuW+oyVaxA=; b=wuF1+J0Rf3KCvRMWho/EdMhNcQPCllusg/SK4bdvq6P8d+9NaHZKL6H7 ImGLhgUhld2D3e+8YvSJ6ZgNptHNT9MlaGjKC7282a2qhZ7/qZ1H2d3KI Nc6a0x7pH3AxFfawwkFhYkuiq5IMn3LXBjUjqG22vJ6Zmnf5ZAvne5hlG U=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-02.qualcomm.com with ESMTP; 24 Feb 2022 03:48:13 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 03:48:12 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Thu, 24 Feb 2022 03:48:12 -0800 Received: from krabica.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Thu, 24 Feb 2022 03:48:11 -0800 From: Tomas Pilar To: CC: Ray Ni , Ard Biesheuvel , Leif Lindholm Subject: [PATCH] MdeModulePkg: Correct high-memory use in NvmExpressDxe Date: Thu, 24 Feb 2022 11:47:44 +0000 Message-ID: <20220224114744.1966974-1-quic_tpilar@quicinc.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Return-Path: quic_tpilar@quicinc.com X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain Delay and move the allocation and mapping of memory that backs the DMA engine in NvmExpress devices to NvmeInit() to ensure that the allocation only happens after the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute is set on the PciIo controller. This ensures that the DMA-backing memory is not forcibly allocated below 4G in system address map. Otherwise the allocation fails on platforms that do not have any memory below the 4G mark and the drive initialisation fails. Cc: Ray Ni Cc: Ard Biesheuvel Cc: Leif Lindholm Signed-off-by: Tomas Pilar --- .../Bus/Pci/NvmExpressDxe/NvmExpress.c | 41 ------------- .../Bus/Pci/NvmExpressDxe/NvmExpressHci.c | 57 ++++++++++++++++--- 2 files changed, 49 insertions(+), 49 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c b/MdeModulePkg= /Bus/Pci/NvmExpressDxe/NvmExpress.c index 9d40f67e8e..cc921756f5 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c @@ -912,8 +912,6 @@ NvmExpressDriverBindingStart ( NVME_CONTROLLER_PRIVATE_DATA *Private;=0D EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;=0D UINT32 NamespaceId;=0D - EFI_PHYSICAL_ADDRESS MappedAddr;=0D - UINTN Bytes;=0D EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *Passthru;=0D =0D DEBUG ((DEBUG_INFO, "NvmExpressDriverBindingStart: start\n"));=0D @@ -959,45 +957,6 @@ NvmExpressDriverBindingStart ( goto Exit;=0D }=0D =0D - //=0D - // 6 x 4kB aligned buffers will be carved out of this buffer.=0D - // 1st 4kB boundary is the start of the admin submission queue.=0D - // 2nd 4kB boundary is the start of the admin completion queue.=0D - // 3rd 4kB boundary is the start of I/O submission queue #1.=0D - // 4th 4kB boundary is the start of I/O completion queue #1.=0D - // 5th 4kB boundary is the start of I/O submission queue #2.=0D - // 6th 4kB boundary is the start of I/O completion queue #2.=0D - //=0D - // Allocate 6 pages of memory, then map it for bus master read and wri= te.=0D - //=0D - Status =3D PciIo->AllocateBuffer (=0D - PciIo,=0D - AllocateAnyPages,=0D - EfiBootServicesData,=0D - 6,=0D - (VOID **)&Private->Buffer,=0D - 0=0D - );=0D - if (EFI_ERROR (Status)) {=0D - goto Exit;=0D - }=0D -=0D - Bytes =3D EFI_PAGES_TO_SIZE (6);=0D - Status =3D PciIo->Map (=0D - PciIo,=0D - EfiPciIoOperationBusMasterCommonBuffer,=0D - Private->Buffer,=0D - &Bytes,=0D - &MappedAddr,=0D - &Private->Mapping=0D - );=0D -=0D - if (EFI_ERROR (Status) || (Bytes !=3D EFI_PAGES_TO_SIZE (6))) {=0D - goto Exit;=0D - }=0D -=0D - Private->BufferPciAddr =3D (UINT8 *)(UINTN)MappedAddr;=0D -=0D Private->Signature =3D NVME_CONTROLLER_PRIVATE_DATA_SI= GNATURE;=0D Private->ControllerHandle =3D Controller;=0D Private->ImageHandle =3D This->DriverBindingHandle;=0D diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c b/MdeModule= Pkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c index ac77afe113..359373300e 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c @@ -718,14 +718,16 @@ NvmeControllerInit ( IN NVME_CONTROLLER_PRIVATE_DATA *Private=0D )=0D {=0D - EFI_STATUS Status;=0D - EFI_PCI_IO_PROTOCOL *PciIo;=0D - UINT64 Supports;=0D - NVME_AQA Aqa;=0D - NVME_ASQ Asq;=0D - NVME_ACQ Acq;=0D - UINT8 Sn[21];=0D - UINT8 Mn[41];=0D + EFI_STATUS Status;=0D + EFI_PCI_IO_PROTOCOL *PciIo;=0D + UINT64 Supports;=0D + NVME_AQA Aqa;=0D + NVME_ASQ Asq;=0D + NVME_ACQ Acq;=0D + UINT8 Sn[21];=0D + UINT8 Mn[41];=0D + UINTN Bytes;=0D + EFI_PHYSICAL_ADDRESS MappedAddr;=0D =0D //=0D // Save original PCI attributes and enable this controller.=0D @@ -777,6 +779,45 @@ NvmeControllerInit ( DEBUG ((DEBUG_WARN, "NvmeControllerInit: failed to enable 64-bit DMA (= %r)\n", Status));=0D }=0D =0D + //=0D + // 6 x 4kB aligned buffers will be carved out of this buffer.=0D + // 1st 4kB boundary is the start of the admin submission queue.=0D + // 2nd 4kB boundary is the start of the admin completion queue.=0D + // 3rd 4kB boundary is the start of I/O submission queue #1.=0D + // 4th 4kB boundary is the start of I/O completion queue #1.=0D + // 5th 4kB boundary is the start of I/O submission queue #2.=0D + // 6th 4kB boundary is the start of I/O completion queue #2.=0D + //=0D + // Allocate 6 pages of memory, then map it for bus master read and write= .=0D + //=0D + Status =3D PciIo->AllocateBuffer (=0D + PciIo,=0D + AllocateAnyPages,=0D + EfiBootServicesData,=0D + 6,=0D + (VOID **)&Private->Buffer,=0D + 0=0D + );=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + Bytes =3D EFI_PAGES_TO_SIZE (6);=0D + Status =3D PciIo->Map (=0D + PciIo,=0D + EfiPciIoOperationBusMasterCommonBuffer,=0D + Private->Buffer,=0D + &Bytes,=0D + &MappedAddr,=0D + &Private->Mapping=0D + );=0D +=0D + if (EFI_ERROR (Status) || (Bytes !=3D EFI_PAGES_TO_SIZE (6))) {=0D + return Status;=0D + }=0D +=0D + Private->BufferPciAddr =3D (UINT8 *)(UINTN)MappedAddr;=0D +=0D //=0D // Read the Controller Capabilities register and verify that the NVM com= mand set is supported=0D //=0D --=20 2.30.2