From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by mx.groups.io with SMTP id smtpd.web10.9809.1645707485179774329 for ; Thu, 24 Feb 2022 04:58:05 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=pJll5M7Y; spf=pass (domain: quicinc.com, ip: 199.106.114.38, mailfrom: quic_tpilar@quicinc.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1645707485; x=1677243485; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=at4TFg8sgP7QgyqNOUN/lqfJL9eeBDDHRL6VgcljMP4=; b=pJll5M7Y4mHrZ+b6PV1JqpUm6WM0Au5jtNrhOOveM17x3f2IeMY/2ftO m3CovepOTDSVDne9SswNcPJJo9HZ8FWlTKnJHpEDVewL8usxBUtBpTGOw RPUY4PnrmICXYTMnjAt2cvHUW3uz8jtaFpzumIhgGSlWF710rzoc9HykE k=; Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-01.qualcomm.com with ESMTP; 24 Feb 2022 04:58:04 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg02-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 04:58:03 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Thu, 24 Feb 2022 04:58:02 -0800 Received: from krabica.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Thu, 24 Feb 2022 04:58:00 -0800 From: "Tomas Pilar (tpilar)" To: CC: Ray Ni , Ard Biesheuvel , Leif Lindholm Subject: [PATCH v2] MdeModulePkg: Correct high-memory use in NvmExpressDxe Date: Thu, 24 Feb 2022 12:57:53 +0000 Message-ID: <20220224125753.2021633-1-quic_tpilar@quicinc.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Return-Path: quic_tpilar@quicinc.com X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain Move the logic that sets EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE Pci=0D attribute to DriverBindingStart() before the memory that backs the=0D DMA engine is allocated.=0D =0D This ensures that the DMA-backing memory is not forcibly allocated=0D below 4G in system address map. Otherwise the allocation fails on=0D platforms that do not have any memory below the 4G mark and the drive=0D initialisation fails.=0D =0D Cc: Ray Ni =0D Cc: Ard Biesheuvel =0D Cc: Leif Lindholm =0D Signed-off-by: Tomas Pilar =0D ---=0D MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c | 13 +++++++++++++=0D MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c | 13 -------------=0D 2 files changed, 13 insertions(+), 13 deletions(-)=0D =0D diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c b/MdeModulePkg= /Bus/Pci/NvmExpressDxe/NvmExpress.c=0D index 9d40f67e8e..1f0fc5bb68 100644=0D --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c=0D +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c=0D @@ -959,6 +959,19 @@ NvmExpressDriverBindingStart (=0D goto Exit;=0D }=0D =0D + //=0D + // Enable 64-bit DMA support in the PCI layer.=0D + //=0D + Status =3D PciIo->Attributes (=0D + PciIo,=0D + EfiPciIoAttributeOperationEnable,=0D + EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE,=0D + NULL=0D + );=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_WARN, "NvmeControllerInit: failed to enable 64-bit DMA= (%r)\n", Status));=0D + }=0D +=0D //=0D // 6 x 4kB aligned buffers will be carved out of this buffer.=0D // 1st 4kB boundary is the start of the admin submission queue.=0D diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c b/MdeModule= Pkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c=0D index ac77afe113..748cb0ba24 100644=0D --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c=0D +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c=0D @@ -764,19 +764,6 @@ NvmeControllerInit (=0D return Status;=0D }=0D =0D - //=0D - // Enable 64-bit DMA support in the PCI layer.=0D - //=0D - Status =3D PciIo->Attributes (=0D - PciIo,=0D - EfiPciIoAttributeOperationEnable,=0D - EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE,=0D - NULL=0D - );=0D - if (EFI_ERROR (Status)) {=0D - DEBUG ((DEBUG_WARN, "NvmeControllerInit: failed to enable 64-bit DMA (= %r)\n", Status));=0D - }=0D -=0D //=0D // Read the Controller Capabilities register and verify that the NVM com= mand set is supported=0D //=0D -- =0D 2.30.2=0D