From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by mx.groups.io with SMTP id smtpd.web10.12537.1645719671785168297 for ; Thu, 24 Feb 2022 08:21:11 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=T7Kkr5Zd; spf=pass (domain: quicinc.com, ip: 129.46.98.28, mailfrom: quic_tpilar@quicinc.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1645719671; x=1677255671; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=rnSNDkG88tL+Db3buMLhL3uDWoAK/oj0decKnwgZ09Q=; b=T7Kkr5Zd2q9lWFtrAyTySbuEwLQGm7R4diWph+oDxFJ52ieH5FV1u0Uf GUaMCYDt96HIFYgxc0R9MVxvK/kf1Expdaw1XPYn/7YKHHTtxKIGrri/A vCtWAvhnoKsM1vWhmDhlLm6SAwnpimCE38ZnzzLQ1Ub33x+j0qkI1DS4/ k=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 24 Feb 2022 08:21:11 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 08:21:10 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Thu, 24 Feb 2022 08:21:10 -0800 Received: from krabica.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Thu, 24 Feb 2022 08:21:08 -0800 From: "Tomas Pilar (tpilar)" To: CC: Ray Ni , Ard Biesheuvel , Leif Lindholm , Hao A Wu , Ard Biesheuvel Subject: [PATCH v4] MdeModulePkg: Correct high-memory use in NvmExpressDxe Date: Thu, 24 Feb 2022 16:21:01 +0000 Message-ID: <20220224162101.2132857-1-quic_tpilar@quicinc.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Return-Path: quic_tpilar@quicinc.com X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain Move the logic that stores starting PCI attributes and sets the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute to DriverBindingStart() before the memory that backs the DMA engine is allocated. This ensures that the DMA-backing memory is not forcibly allocated below 4G in system address map. Otherwise the allocation fails on platforms that do not have any memory below the 4G mark and the drive initialisation fails. Leave the PCI device enabling attribute logic in NvmeControllerInit() to ensure that the device is re-enabled on reset in case it was disabled via PCI attributes. Cc: Ray Ni Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Hao A Wu Reviewed-by: Ard Biesheuvel Signed-off-by: Tomas Pilar --- MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c | 27 ++++++++++++++++++= ++ MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c | 26 +------------------ 2 files changed, 28 insertions(+), 25 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c b/MdeModulePkg= /Bus/Pci/NvmExpressDxe/NvmExpress.c index 9d40f67e8e..5a1eda8e8d 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c @@ -959,6 +959,33 @@ NvmExpressDriverBindingStart ( goto Exit;=0D }=0D =0D + //=0D + // Save original PCI attributes=0D + //=0D + Status =3D PciIo->Attributes (=0D + PciIo,=0D + EfiPciIoAttributeOperationGet,=0D + 0,=0D + &Private->PciAttributes=0D + );=0D +=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + //=0D + // Enable 64-bit DMA support in the PCI layer.=0D + //=0D + Status =3D PciIo->Attributes (=0D + PciIo,=0D + EfiPciIoAttributeOperationEnable,=0D + EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE,=0D + NULL=0D + );=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_WARN, "NvmExpressDriverBindingStart: failed to enable = 64-bit DMA (%r)\n", Status));=0D + }=0D +=0D //=0D // 6 x 4kB aligned buffers will be carved out of this buffer.=0D // 1st 4kB boundary is the start of the admin submission queue.=0D diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c b/MdeModule= Pkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c index ac77afe113..d87212ffb2 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c @@ -728,20 +728,9 @@ NvmeControllerInit ( UINT8 Mn[41];=0D =0D //=0D - // Save original PCI attributes and enable this controller.=0D + // Enable this controller.=0D //=0D PciIo =3D Private->PciIo;=0D - Status =3D PciIo->Attributes (=0D - PciIo,=0D - EfiPciIoAttributeOperationGet,=0D - 0,=0D - &Private->PciAttributes=0D - );=0D -=0D - if (EFI_ERROR (Status)) {=0D - return Status;=0D - }=0D -=0D Status =3D PciIo->Attributes (=0D PciIo,=0D EfiPciIoAttributeOperationSupported,=0D @@ -764,19 +753,6 @@ NvmeControllerInit ( return Status;=0D }=0D =0D - //=0D - // Enable 64-bit DMA support in the PCI layer.=0D - //=0D - Status =3D PciIo->Attributes (=0D - PciIo,=0D - EfiPciIoAttributeOperationEnable,=0D - EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE,=0D - NULL=0D - );=0D - if (EFI_ERROR (Status)) {=0D - DEBUG ((DEBUG_WARN, "NvmeControllerInit: failed to enable 64-bit DMA (= %r)\n", Status));=0D - }=0D -=0D //=0D // Read the Controller Capabilities register and verify that the NVM com= mand set is supported=0D //=0D --=20 2.30.2