From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.17836.1646036244358797905 for ; Mon, 28 Feb 2022 00:17:24 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=Tf8kIRTf; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: min.m.xu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646036244; x=1677572244; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YjeAbQ172uZdyWsMhRc3bYwi+rkmX6Yu0BHMT4OQ7oY=; b=Tf8kIRTfdODa9yOehgUiv0dkkjEdbe160fxYCl8gSlas8SCzf2hoh3ST vllg+K2BNbxAZuBy2l1m3urGu309TuuFPaKb7fDqjEHEge6XoV6IiClF0 m34nfaEA6dTniBx/o0GTt8iExsWRjA/oXN1soH8CQGeGOGzgXWECC27Ee NMNXaCuro+g6l7o0SA7hebkpT+vEb7fjCoBTKj8YR+833lcwb+JGZS97Y oaVd9MikApngkgH1THVEbYq+QoLTV0QgiCpPs8mgBo5S1MVK5pXzdfUmZ OCSa7stACmlg7t2MXmWV3TyhmiUSQAvnfDM5M9nWMk471Hk7BaMZa2Mce Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10271"; a="339268980" X-IronPort-AV: E=Sophos;i="5.90,142,1643702400"; d="scan'208";a="339268980" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2022 00:17:22 -0800 X-IronPort-AV: E=Sophos;i="5.90,142,1643702400"; d="scan'208";a="550140153" Received: from mxu9-mobl1.ccr.corp.intel.com ([10.238.2.184]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2022 00:17:16 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Michael D Kinney , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [PATCH V4 06/10] OvmfPkg: Update TdxDxe to set TDX PCDs Date: Mon, 28 Feb 2022 16:16:27 +0800 Message-Id: <20220228081631.681-7-min.m.xu@intel.com> X-Mailer: git-send-email 2.29.2.windows.2 In-Reply-To: <20220228081631.681-1-min.m.xu@intel.com> References: <20220228081631.681-1-min.m.xu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429 TDX_PEI_LESS_BOOT indicates the boot without PEI phase. In this case settings in EFI_HOB_PLATFORM_INFO should be set to its according PCDs. TdxDxe driver is workable for both Legacy guest and Tdx guest. It is because for Legacy guest (in PEI-less boot) there should be a place to set the PCDs based on EFI_HOB_PLATFORM_INFO hob. TdxDxe driver is the right place to do this work. Cc: Michael D Kinney Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- OvmfPkg/TdxDxe/TdxDxe.c | 69 ++++++++++++++++++++++++++++++++++++++- OvmfPkg/TdxDxe/TdxDxe.inf | 5 +++ 2 files changed, 73 insertions(+), 1 deletion(-) diff --git a/OvmfPkg/TdxDxe/TdxDxe.c b/OvmfPkg/TdxDxe/TdxDxe.c index da392a492c63..6c93fac4558a 100644 --- a/OvmfPkg/TdxDxe/TdxDxe.c +++ b/OvmfPkg/TdxDxe/TdxDxe.c @@ -24,12 +24,68 @@ #include #include #include +#include #include #include #include #include #include +VOID +SetPcdSettings ( + EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + RETURN_STATUS PcdStatus; + + PcdStatus = PcdSet64S (PcdConfidentialComputingGuestAttr, PlatformInfoHob->PcdConfidentialComputingGuestAttr); + ASSERT_RETURN_ERROR (PcdStatus); + PcdStatus = PcdSetBoolS (PcdSetNxForStack, PlatformInfoHob->PcdSetNxForStack); + ASSERT_RETURN_ERROR (PcdStatus); + PcdStatus = PcdSetBoolS (PcdIa32EferChangeAllowed, PlatformInfoHob->PcdIa32EferChangeAllowed); + ASSERT_RETURN_ERROR (PcdStatus); + + DEBUG (( + DEBUG_INFO, + "HostBridgeDevId=0x%x, CCAttr=0x%x, SetNxForStack=%x, Ia32EferChangeAllowed=%x\n", + PlatformInfoHob->HostBridgePciDevId, + PlatformInfoHob->PcdConfidentialComputingGuestAttr, + PlatformInfoHob->PcdSetNxForStack, + PlatformInfoHob->PcdIa32EferChangeAllowed + )); + + PcdStatus = PcdSet32S (PcdCpuBootLogicalProcessorNumber, PlatformInfoHob->PcdCpuBootLogicalProcessorNumber); + ASSERT_RETURN_ERROR (PcdStatus); + PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, PlatformInfoHob->PcdCpuMaxLogicalProcessorNumber); + + ASSERT_RETURN_ERROR (PcdStatus); + DEBUG (( + DEBUG_INFO, + "MaxCpuCount=0x%x, BootCpuCount=0x%x\n", + PlatformInfoHob->PcdCpuMaxLogicalProcessorNumber, + PlatformInfoHob->PcdCpuBootLogicalProcessorNumber + )); + + if (TdIsEnabled ()) { + PcdStatus = PcdSet64S (PcdTdxSharedBitMask, TdSharedPageMask ()); + ASSERT_RETURN_ERROR (PcdStatus); + DEBUG ((DEBUG_INFO, "TdxSharedBitMask=0x%llx\n", PcdGet64 (PcdTdxSharedBitMask))); + } else { + PcdStatus = PcdSet64S (PcdPciMmio64Base, PlatformInfoHob->PcdPciMmio64Base); + ASSERT_RETURN_ERROR (PcdStatus); + PcdStatus = PcdSet64S (PcdPciMmio64Size, PlatformInfoHob->PcdPciMmio64Size); + ASSERT_RETURN_ERROR (PcdStatus); + PcdStatus = PcdSet64S (PcdPciMmio32Base, PlatformInfoHob->PcdPciMmio32Base); + ASSERT_RETURN_ERROR (PcdStatus); + PcdStatus = PcdSet64S (PcdPciMmio32Size, PlatformInfoHob->PcdPciMmio32Size); + ASSERT_RETURN_ERROR (PcdStatus); + PcdStatus = PcdSet64S (PcdPciIoBase, PlatformInfoHob->PcdPciIoBase); + ASSERT_RETURN_ERROR (PcdStatus); + PcdStatus = PcdSet64S (PcdPciIoSize, PlatformInfoHob->PcdPciIoSize); + ASSERT_RETURN_ERROR (PcdStatus); + } +} + /** Location of resource hob matching type and starting address @@ -187,8 +243,19 @@ TdxDxeEntryPoint ( PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, PlatformInfo->HostBridgePciDevId); ASSERT_RETURN_ERROR (PcdStatus); + #ifdef TDX_PEI_LESS_BOOT + // + // For Pei-less boot, PlatformInfo contains more information and + // need to set PCDs based on these information. + // + SetPcdSettings (PlatformInfo); + #endif + if (!TdIsEnabled ()) { - return EFI_UNSUPPORTED; + // + // If it is Non-Td guest, we're done. + // + return EFI_SUCCESS; } SetMmioSharedBit (); diff --git a/OvmfPkg/TdxDxe/TdxDxe.inf b/OvmfPkg/TdxDxe/TdxDxe.inf index b5976ab3ceba..4d169ae61129 100644 --- a/OvmfPkg/TdxDxe/TdxDxe.inf +++ b/OvmfPkg/TdxDxe/TdxDxe.inf @@ -60,5 +60,10 @@ gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber + gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress + gEfiMdeModulePkgTokenSpaceGuid.PcdIa32EferChangeAllowed + gEfiMdePkgTokenSpaceGuid.PcdConfidentialComputingGuestAttr + gEfiMdeModulePkgTokenSpaceGuid.PcdTdxSharedBitMask + gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack -- 2.29.2.windows.2