From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mx.groups.io with SMTP id smtpd.web10.5530.1646212796036188164 for ; Wed, 02 Mar 2022 01:19:56 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=YhACJIYw; spf=pass (domain: intel.com, ip: 192.55.52.136, mailfrom: yu.pu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646212796; x=1677748796; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=L2B5ZHfl3q4WMhJDJF0Ln/ggtEwriFHDAqv3XKBsVaw=; b=YhACJIYwk9W/LJiqNgDGy96Wr/s/onuAWXWBOkeINQrWKWI0Kwkd1euz AWyAxegqW4exAgCN+h8prvheESIVKMfJ4sp5lx+vMHyiXyj1XUKJTuyuX 73hCjXSF/rBQVtpWp0AysEIpxvC6NWHMD1BHYyClNiGAHSWIppKDGEIsn 4N2ucVfE669LRgUmONE6FzTBh2LYr+9/gZgGmUaLgspsrGxmT+Hap+TG4 ATLvXQsl2n6OimNMIomtv2suQbWOPMvslVV+afzL+mG4M+eYPzqX04sXi DTwpD91gEP3TGo/hgF8t2CMM5FzhmmkfIzOBzrAMhOYlVm0fSofRkgVK2 g==; X-IronPort-AV: E=McAfee;i="6200,9189,10273"; a="233324159" X-IronPort-AV: E=Sophos;i="5.90,148,1643702400"; d="scan'208";a="233324159" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2022 01:19:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,148,1643702400"; d="scan'208";a="641630294" Received: from shwdeopenlab704.ccr.corp.intel.com ([10.239.182.239]) by orsmga004.jf.intel.com with ESMTP; 02 Mar 2022 01:19:53 -0800 From: Yu Pu To: devel@edk2.groups.io Cc: Yu Pu , Eric Dong , Ray Ni Subject: [PATCH v1 1/7] UefiCpuPackage: Add APIs for CPU physical address mask calculation Date: Wed, 2 Mar 2022 17:18:53 +0800 Message-Id: <20220302091859.2783-2-yu.pu@intel.com> X-Mailer: git-send-email 2.30.0.windows.2 In-Reply-To: <20220302091859.2783-1-yu.pu@intel.com> References: <20220302091859.2783-1-yu.pu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3394 Add API named GetPhysicalAddressBits() for CPU physical address mask calculation, and remove the duplicated code in UefiCpuPackage. Cc: Eric Dong Cc: Ray Ni Signed-off-by: Yu Pu --- UefiCpuPkg/CpuDxe/CpuDxe.c | 16 +------ UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c | 47 ++++++++++++++++++= ++ UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 9 +--- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 9 +--- UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 9 +--- UefiCpuPkg/Include/Library/UefiCpuLib.h | 17 +++++++ 6 files changed, 70 insertions(+), 37 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.c b/UefiCpuPkg/CpuDxe/CpuDxe.c index 00f3cb09572c..8aca1bf72b4c 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.c +++ b/UefiCpuPkg/CpuDxe/CpuDxe.c @@ -503,21 +503,7 @@ InitializeMtrrMask ( VOID=0D )=0D {=0D - UINT32 RegEax;=0D - UINT8 PhysicalAddressBits;=0D -=0D - AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);=0D -=0D - if (RegEax >=3D 0x80000008) {=0D - AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);=0D -=0D - PhysicalAddressBits =3D (UINT8)RegEax;=0D - } else {=0D - PhysicalAddressBits =3D 36;=0D - }=0D -=0D - mValidMtrrBitsMask =3D LShiftU64 (1, PhysicalAddressBits) - 1;=0D - mValidMtrrAddressMask =3D mValidMtrrBitsMask & 0xfffffffffffff000ULL;=0D + GetPhysicalAddressBits(&mValidMtrrBitsMask, &mValidMtrrAddressMask);=0D }=0D =0D /**=0D diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c b/UefiCpuPk= g/Library/BaseUefiCpuLib/BaseUefiCpuLib.c index 5d925bc273f8..bb1343f3cd21 100644 --- a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c +++ b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c @@ -79,3 +79,50 @@ GetCpuSteppingId ( =0D return (UINT8)Eax.Bits.SteppingId;=0D }=0D +=0D +/**=0D + Get the physical address width supported by the processor.=0D + @param[out] ValidAddressMask Bitmask with valid address bits se= t to=0D + one; other bits are clear. Optiona= l=0D + parameter.=0D + @param[out] ValidPageBaseAddressMask Bitmask with valid page base addre= ss=0D + bits set to one; other bits are cl= ear.=0D + Optional parameter.=0D + @return The physical address width supported by the processor.=0D +**/=0D +UINT8=0D +EFIAPI=0D +GetPhysicalAddressBits (=0D + OUT UINT64 *ValidAddressMask OPTIONAL,=0D + OUT UINT64 *ValidPageBaseAddressMask OPTIONAL=0D + )=0D +{=0D + UINT32 MaxExtendedFunction;=0D + CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize;=0D + UINT64 AddressMask;=0D + UINT64 PageBaseAddressMask;=0D +=0D + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunction, NULL, NULL, NUL= L);=0D + if (MaxExtendedFunction >=3D CPUID_VIR_PHY_ADDRESS_SIZE) {=0D + AsmCpuid (=0D + CPUID_VIR_PHY_ADDRESS_SIZE,=0D + &VirPhyAddressSize.Uint32,=0D + NULL,=0D + NULL,=0D + NULL=0D + );=0D + } else {=0D + VirPhyAddressSize.Bits.PhysicalAddressBits =3D 36;=0D + }=0D +=0D + AddressMask =3D LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits= ) - 1;=0D + PageBaseAddressMask =3D AddressMask & ~(UINT64)0xFFF;=0D +=0D + if (ValidAddressMask !=3D NULL) {=0D + *ValidAddressMask =3D AddressMask;=0D + }=0D + if (ValidPageBaseAddressMask !=3D NULL) {=0D + *ValidPageBaseAddressMask =3D PageBaseAddressMask;=0D + }=0D + return (UINT8)VirPhyAddressSize.Bits.PhysicalAddressBits;=0D +}=0D diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c b/UefiCpuPkg/Lib= rary/SmmCpuFeaturesLib/SmmStm.c index 4e8f897f5e9c..ec7cd4013132 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c @@ -15,6 +15,7 @@ #include =0D #include =0D #include =0D +#include =0D #include =0D #include =0D #include =0D @@ -330,13 +331,7 @@ SmmCpuFeaturesInstallSmiHandler ( if (Hob !=3D NULL) {=0D Psd->PhysicalAddressBits =3D ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace;= =0D } else {=0D - AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);=0D - if (RegEax >=3D 0x80000008) {=0D - AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);=0D - Psd->PhysicalAddressBits =3D (UINT8)RegEax;=0D - } else {=0D - Psd->PhysicalAddressBits =3D 36;=0D - }=0D + Psd->PhysicalAddressBits =3D GetPhysicalAddressBits (NULL, NULL);=0D }=0D =0D if (!mStmConfigurationTableInitialized) {=0D diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuD= xeSmm/X64/PageTbl.c index 538394f23910..de1385a86948 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -194,7 +194,6 @@ CalculateMaximumSupportAddress ( VOID=0D )=0D {=0D - UINT32 RegEax;=0D UINT8 PhysicalAddressBits;=0D VOID *Hob;=0D =0D @@ -205,13 +204,7 @@ CalculateMaximumSupportAddress ( if (Hob !=3D NULL) {=0D PhysicalAddressBits =3D ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace;=0D } else {=0D - AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);=0D - if (RegEax >=3D 0x80000008) {=0D - AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);=0D - PhysicalAddressBits =3D (UINT8)RegEax;=0D - } else {=0D - PhysicalAddressBits =3D 36;=0D - }=0D + PhysicalAddressBits =3D GetPhysicalAddressBits (NULL, NULL);=0D }=0D =0D return PhysicalAddressBits;=0D diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c b/UefiCpuPkg= /Universal/Acpi/S3Resume2Pei/S3Resume.c index 8419a4e32acb..1017f0316093 100644 --- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c +++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c @@ -42,6 +42,7 @@ #include =0D #include =0D #include =0D +#include =0D =0D /**=0D This macro aligns the address of a variable with auto storage=0D @@ -646,13 +647,7 @@ RestoreS3PageTables ( if (Hob !=3D NULL) {=0D PhysicalAddressBits =3D ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace;=0D } else {=0D - AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);=0D - if (RegEax >=3D 0x80000008) {=0D - AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);=0D - PhysicalAddressBits =3D (UINT8)RegEax;=0D - } else {=0D - PhysicalAddressBits =3D 36;=0D - }=0D + PhysicalAddressBits =3D GetPhysicalAddressBits (NULL, NULL);=0D }=0D =0D //=0D diff --git a/UefiCpuPkg/Include/Library/UefiCpuLib.h b/UefiCpuPkg/Include/L= ibrary/UefiCpuLib.h index 0ff4a35774c1..dabed95ab38a 100644 --- a/UefiCpuPkg/Include/Library/UefiCpuLib.h +++ b/UefiCpuPkg/Include/Library/UefiCpuLib.h @@ -62,4 +62,21 @@ GetCpuSteppingId ( VOID=0D );=0D =0D +/**=0D + Get the physical address width supported by the processor.=0D + @param[out] ValidAddressMask Bitmask with valid address bits se= t to=0D + one; other bits are clear. Optiona= l=0D + parameter.=0D + @param[out] ValidPageBaseAddressMask Bitmask with valid page base addre= ss=0D + bits set to one; other bits are cl= ear.=0D + Optional parameter.=0D + @return The physical address width supported by the processor.=0D +**/=0D +UINT8=0D +EFIAPI=0D +GetPhysicalAddressBits (=0D + OUT UINT64 *ValidAddressMask OPTIONAL,=0D + OUT UINT64 *ValidPageBaseAddressMask OPTIONAL=0D + );=0D +=0D #endif=0D --=20 2.30.0.windows.2