From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web11.6942.1647586017540268411 for ; Thu, 17 Mar 2022 23:46:57 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=E8fTRSWd; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=0076e51d84=abner.chang@hpe.com) Received: from pps.filterd (m0148663.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 22I5W92w002163 for ; Fri, 18 Mar 2022 06:46:57 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : content-transfer-encoding : mime-version; s=pps0720; bh=/vVg94h/XPlD6GphLXm+EQszGYvuM3f67yC3b1LUmtk=; b=E8fTRSWddgmIBqUB6mO10Rc4uEJ08HcZ+FBebmIoxNo8H8PjWaMdex+GwR/yPVo4AGLV RqxlYwFUMpHs4MA+lkdX4g0Zr/cv3RWlI/MykTaKR3wCoWZjMgIZFFJp83NftOG4ySD3 Ddv1+RsDqTVDmZh1rUTTzN3AaNZezwnJs03jsID8Fhs5I57NjyvEEfG4zlEzqcjpuuDS lIcPk+XKZfNk388rJvVNcB4u2mCbg+ZPyYIDsJw9uih7SwWDvdn6M6b9/QHaMzVWmtOk E+sVmePPdVPPflM/h6wbOrecJQbqqlt9Im1fdCBTg1k78B9XMb5gRVy4xPyOQxlRskn+ PA== Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0a-002e3701.pphosted.com (PPS) with ESMTPS id 3eve3vk48d-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 18 Mar 2022 06:46:57 +0000 Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id 495D05B for ; Fri, 18 Mar 2022 06:46:56 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 704094A; Fri, 18 Mar 2022 06:46:55 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [PATCH 0/6] [RFC] Rework UefiCpuPkg Date: Fri, 18 Mar 2022 13:43:16 +0800 Message-Id: <20220318054322.11520-1-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 X-Proofpoint-ORIG-GUID: 7TzQstvWdFJCUbFWjw3AYgo-4NNegoSq X-Proofpoint-GUID: 7TzQstvWdFJCUbFWjw3AYgo-4NNegoSq X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.850,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-18_06,2022-03-15_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=416 suspectscore=0 bulkscore=0 malwarescore=0 phishscore=0 adultscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 mlxscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2203180034 Content-Transfer-Encoding: 8bit https://bugzilla.tianocore.org/show_bug.cgi?id=3860 This is the project having rework on UefiCpuPkg in order to support a variety of processor architectures. Some modules under UefiCpuPkg are required to be abstract for the different archs. The first step is to classify UefiCpuPkg modules to IA32 and X64 sections in DSC file (Patch 1/6). Move the module to Common section later if more than one archs can leverage the same module (such as Patch 3/6 for BaseUefiCpuLib). Abner Chang (6): [RFC] UefiCpuPkg: Classify IA32/X64 modules in DSC file [RFC] UefiCpuPkg/Include: Add header files of RISC-V processor architecture [RFC] UefiCpuPkg/BaseUefiCpuLib: Add RISC-V RISCV64 instace [RFC] UefiCpuPkg/RiscVOpensbLib: Add opensbi submodule [RFC] UefiCpuPkg/Library: Add RiscVOpensbiLib [RFC] UefiCpuPkg: Update YAML file for RISC-V arch UefiCpuPkg/UefiCpuPkg.dec | 12 +- UefiCpuPkg/UefiCpuPkg.dsc | 45 +++-- .../Library/BaseUefiCpuLib/BaseUefiCpuLib.inf | 8 +- .../RiscVOpensbiLib/RiscVOpensbiLib.inf | 89 ++++++++++ .../Include/IndustryStandard/RISC-V/RiscV.h | 162 ++++++++++++++++++ .../IndustryStandard/RISC-V/RiscVOpensbi.h | 62 +++++++ .../Include/Library/RISC-V/RiscVCpuLib.h | 118 +++++++++++++ UefiCpuPkg/Include/RISC-V/OpensbiTypes.h | 82 +++++++++ UefiCpuPkg/Include/RISC-V/RiscVImpl.h | 87 ++++++++++ .gitmodules | 45 ++--- BaseTools/Conf/tools_def.template | 2 +- .../Library/BaseUefiCpuLib/BaseUefiCpuLib.uni | 5 +- .../Library/BaseUefiCpuLib/RISCV64/Cpu.S | 143 ++++++++++++++++ .../Library/RISC-V/RiscVOpensbiLib/opensbi | 1 + UefiCpuPkg/UefiCpuPkg.ci.yaml | 61 ++++++- 15 files changed, 877 insertions(+), 45 deletions(-) create mode 100644 UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf create mode 100644 UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscV.h create mode 100644 UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscVOpensbi.h create mode 100644 UefiCpuPkg/Include/Library/RISC-V/RiscVCpuLib.h create mode 100644 UefiCpuPkg/Include/RISC-V/OpensbiTypes.h create mode 100644 UefiCpuPkg/Include/RISC-V/RiscVImpl.h create mode 100644 UefiCpuPkg/Library/BaseUefiCpuLib/RISCV64/Cpu.S create mode 160000 UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/opensbi -- 2.31.1