From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web12.6742.1647586033467642544 for ; Thu, 17 Mar 2022 23:47:13 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=JJcp/gu1; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: hpe.com, ip: 148.163.143.35, mailfrom: prvs=0076e51d84=abner.chang@hpe.com) Received: from pps.filterd (m0134425.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 22I0WSE9017538; Fri, 18 Mar 2022 06:47:11 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : content-transfer-encoding : mime-version; s=pps0720; bh=kO54MHK6abB+aGb23Vtewbi49zuRDCvuPmr+w6LmuF0=; b=JJcp/gu1lRnetbMzD9d6GMEsaSCzqpjIUij9vOltaGXeWX07kXzpc19hyI+6OVMOih7h d7oOtw2l8svTMLoS1G96nRnuSWGsJ2ZehK8fPibYndDLVBkZ30K6drL+QbELnnCQlSqt wjIa0QmOpEMzizgJsq/v7RVIPc9tlWpFFOr3u49hPG0nQM//3CYVJbXM5FHaXsiXgdjl 2tcl8FN0n6RwEq38gHbvDs6/bD0CiWjvq0L/YkWRvYSh5m451MNe8/BxLXT5F9k8H8QG jlxJbm/87DAswrbZ8Lr0o813QOhGOx6wCaiTezXxGfUS2s63BRexknrty2h7NIrZVnv+ Sg== Received: from g4t3425.houston.hpe.com (g4t3425.houston.hpe.com [15.241.140.78]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3eve38u9kd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 18 Mar 2022 06:47:11 +0000 Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3425.houston.hpe.com (Postfix) with ESMTP id B94D58D; Fri, 18 Mar 2022 06:47:10 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 524B04B; Fri, 18 Mar 2022 06:47:08 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Eric Dong , Ray Ni , Rahul Kumar , Sunil V L , Andrew Fish , Leif Lindholm , Michael D Kinney , Chao Li Subject: [PATCH 5/6] [RFC] UefiCpuPkg/Library: Add RiscVOpensbiLib Date: Fri, 18 Mar 2022 13:43:21 +0800 Message-Id: <20220318054322.11520-6-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220318054322.11520-1-abner.chang@hpe.com> References: <20220318054322.11520-1-abner.chang@hpe.com> X-Proofpoint-ORIG-GUID: mOXCWNG3gSpD7LGUpgl4koH25k_f2Cu_ X-Proofpoint-GUID: mOXCWNG3gSpD7LGUpgl4koH25k_f2Cu_ X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.850,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-18_06,2022-03-15_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 priorityscore=1501 phishscore=0 malwarescore=0 mlxlogscore=999 bulkscore=0 mlxscore=0 impostorscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2203180034 Content-Transfer-Encoding: quoted-printable https://bugzilla.tianocore.org/show_bug.cgi?id=3D3860 (This is migrated from edk2-platforms:Silicon/RISC-V) EDK2 RISC-V OpenSBI library which pull in external source files under UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/opensbi to the build process. Signed-off-by: Abner Chang Co-authored-by: Daniel Schaefer Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Sunil V L Cc: Andrew Fish Cc: Leif Lindholm Cc: Michael D Kinney Cc: Chao Li --- UefiCpuPkg/UefiCpuPkg.dec | 12 ++- UefiCpuPkg/UefiCpuPkg.dsc | 6 ++ .../RiscVOpensbiLib/RiscVOpensbiLib.inf | 89 +++++++++++++++++++ .../IndustryStandard/RISC-V/RiscVOpensbi.h | 62 +++++++++++++ UefiCpuPkg/Include/RISC-V/OpensbiTypes.h | 82 +++++++++++++++++ BaseTools/Conf/tools_def.template | 2 +- 6 files changed, 250 insertions(+), 3 deletions(-) create mode 100644 UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiL= ib.inf create mode 100644 UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscVOpensbi= .h create mode 100644 UefiCpuPkg/Include/RISC-V/OpensbiTypes.h diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 525cde4634..8e85d242a3 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -1,7 +1,8 @@ ## @file UefiCpuPkg.dec=0D # This Package provides UEFI compatible CPU modules and libraries.=0D #=0D -# Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.
=0D +# Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -14,9 +15,16 @@ PACKAGE_GUID =3D 2171df9b-0d39-45aa-ac37-2de190010d23= =0D PACKAGE_VERSION =3D 0.90=0D =0D -[Includes]=0D +[Includes.common]=0D Include=0D =0D +[Includes.RISCV64]=0D + Include/Library=0D + Library/RISC-V/RiscVOpensbiLib/opensbi # OpenSBI header file ref= erence ("include/sbi/...")=0D + Library/RISC-V/RiscVOpensbiLib/opensbi/include # Header file reference f= rom opensbi files, ("sbi/...")=0D + Library/RISC-V/RiscVOpensbiLib/opensbi/platform/generic/include # Header= file reference from opensbi files, ("sbi/...")=0D +=0D +=0D [LibraryClasses]=0D ## @libraryclass Defines some routines that are generic for IA32 famil= y CPU=0D ## to be UEFI specification compliant.=0D diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 50c9fc294c..374e951f29 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -66,6 +66,9 @@ MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf=0D SmmCpuRendezvousLib|UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezv= ousLib.inf=0D =0D +[LibraryClasses.RISCV64]=0D + RiscVOpensbiLib|UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLi= b.inf=0D +=0D [LibraryClasses.common.SEC]=0D HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf=0D MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf=0D @@ -185,5 +188,8 @@ UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf=0D UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.inf=0D =0D +[Components.RISCV64]=0D + UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf=0D +=0D [BuildOptions]=0D *_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES=0D diff --git a/UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf = b/UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf new file mode 100644 index 0000000000..54eed050d4 --- /dev/null +++ b/UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf @@ -0,0 +1,89 @@ +## @file=0D +# RISC-V Opensbi Library Instance.=0D +#=0D +# Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x0001001b=0D + BASE_NAME =3D RiscVOpensbiLib=0D + FILE_GUID =3D 6EF0C812-66F6-11E9-93CE-3F5D5F0DF0A7=0D + MODULE_TYPE =3D BASE=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D RiscVOpensbiLib=0D +=0D +[Sources]=0D + opensbi/lib/sbi/riscv_asm.c=0D + opensbi/lib/sbi/riscv_atomic.c=0D + opensbi/lib/sbi/riscv_hardfp.S=0D + opensbi/lib/sbi/riscv_locks.c=0D + opensbi/lib/sbi/sbi_bitmap.c=0D + opensbi/lib/sbi/sbi_bitops.c=0D + opensbi/lib/sbi/sbi_console.c=0D + opensbi/lib/sbi/sbi_domain.c=0D + opensbi/lib/sbi/sbi_ecall.c=0D + opensbi/lib/sbi/sbi_ecall_base.c=0D + opensbi/lib/sbi/sbi_ecall_hsm.c=0D + opensbi/lib/sbi/sbi_ecall_legacy.c=0D + opensbi/lib/sbi/sbi_ecall_replace.c=0D + opensbi/lib/sbi/sbi_ecall_vendor.c=0D + opensbi/lib/sbi/sbi_emulate_csr.c=0D + opensbi/lib/sbi/sbi_fifo.c=0D + opensbi/lib/sbi/sbi_hart.c=0D + opensbi/lib/sbi/sbi_math.c=0D + opensbi/lib/sbi/sbi_hfence.S=0D + opensbi/lib/sbi/sbi_hsm.c=0D + opensbi/lib/sbi/sbi_illegal_insn.c=0D + opensbi/lib/sbi/sbi_init.c=0D + opensbi/lib/sbi/sbi_ipi.c=0D + opensbi/lib/sbi/sbi_misaligned_ldst.c=0D + opensbi/lib/sbi/sbi_platform.c=0D + opensbi/lib/sbi/sbi_scratch.c=0D + opensbi/lib/sbi/sbi_string.c=0D + opensbi/lib/sbi/sbi_system.c=0D + opensbi/lib/sbi/sbi_timer.c=0D + opensbi/lib/sbi/sbi_tlb.c=0D + opensbi/lib/sbi/sbi_trap.c=0D + opensbi/lib/sbi/sbi_unpriv.c=0D + opensbi/lib/sbi/sbi_expected_trap.S=0D +=0D + opensbi/lib/utils/fdt/fdt_helper.c=0D + opensbi/lib/utils/fdt/fdt_fixup.c=0D + opensbi/lib/utils/fdt/fdt_domain.c=0D + opensbi/lib/utils/ipi/fdt_ipi.c=0D + opensbi/lib/utils/ipi/aclint_mswi.c=0D + opensbi/lib/utils/ipi/fdt_ipi_mswi.c=0D + opensbi/lib/utils/irqchip/fdt_irqchip.c=0D + opensbi/lib/utils/irqchip/fdt_irqchip_plic.c=0D + opensbi/lib/utils/irqchip/plic.c=0D + opensbi/lib/utils/reset/fdt_reset.c=0D + opensbi/lib/utils/reset/fdt_reset_htif.c=0D + opensbi/lib/utils/reset/fdt_reset_sifive.c=0D + opensbi/lib/utils/reset/fdt_reset_thead.c=0D + opensbi/lib/utils/reset/fdt_reset_thead_asm.S=0D + opensbi/lib/utils/serial/fdt_serial.c=0D + opensbi/lib/utils/serial/fdt_serial_htif.c=0D + opensbi/lib/utils/serial/fdt_serial_shakti.c=0D + opensbi/lib/utils/serial/fdt_serial_sifive.c=0D + opensbi/lib/utils/serial/fdt_serial_uart8250.c=0D + opensbi/lib/utils/serial/fdt_serial_gaisler.c=0D + opensbi/lib/utils/serial/gaisler-uart.c=0D + opensbi/lib/utils/serial/shakti-uart.c=0D + opensbi/lib/utils/serial/sifive-uart.c=0D + opensbi/lib/utils/serial/uart8250.c=0D + opensbi/lib/utils/sys/htif.c=0D + opensbi/lib/utils/sys/sifive_test.c=0D + opensbi/lib/utils/timer/fdt_timer.c=0D + opensbi/lib/utils/timer/aclint_mtimer.c=0D + opensbi/lib/utils/timer/fdt_timer_mtimer.c=0D +=0D +[Packages]=0D + EmbeddedPkg/EmbeddedPkg.dec # For libfdt.=0D + MdePkg/MdePkg.dec=0D + UefiCpuPkg/UefiCpuPkg.dec=0D +=0D +[BuildOptions]=0D + GCC:*_*_*_PP_FLAGS =3D -D__ASSEMBLY__=0D diff --git a/UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscVOpensbi.h b/Ue= fiCpuPkg/Include/IndustryStandard/RISC-V/RiscVOpensbi.h new file mode 100644 index 0000000000..db57aeeb37 --- /dev/null +++ b/UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscVOpensbi.h @@ -0,0 +1,62 @@ +/** @file=0D + SBI inline function calls.=0D +=0D + Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef EDK2_SBI_H_=0D +#define EDK2_SBI_H_=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#define RISC_V_MAX_HART_SUPPORTED SBI_HARTMASK_MAX_BITS=0D +=0D +typedef=0D +VOID=0D +(EFIAPI *RISCV_HART_SWITCH_MODE)(=0D + IN UINTN FuncArg0,=0D + IN UINTN FuncArg1,=0D + IN UINTN NextAddr,=0D + IN UINTN NextMode,=0D + IN BOOLEAN NextVirt=0D + );=0D +=0D +//=0D +// Keep the structure member in 64-bit alignment.=0D +//=0D +typedef struct {=0D + UINT64 IsaExtensionSupported; // The ISA extension th= is core supported.=0D + RISCV_UINT128 MachineVendorId; // Machine vendor ID=0D + RISCV_UINT128 MachineArchId; // Machine Architecture= ID=0D + RISCV_UINT128 MachineImplId; // Machine Implementati= on ID=0D + RISCV_HART_SWITCH_MODE HartSwitchMode; // OpenSBI's function t= o switch the mode of a hart=0D +} EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC;=0D +#define FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE (64 * 8) // This is the size = of EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC=0D + // structure. Referr= ed by both C code and assembly code.=0D +=0D +typedef struct {=0D + UINT64 BootHartId;=0D + VOID *PeiServiceTable; // PEI = Service table=0D + UINT64 FlattenedDeviceTree; // Poin= ter to Flattened Device tree=0D + UINT64 SecPeiHandOffData; // This= is EFI_SEC_PEI_HAND_OFF passed to PEI Core.=0D + EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HAR= T_SUPPORTED];=0D +} EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT;=0D +=0D +//=0D +// Typedefs of OpenSBI type to make them conform to EDK2 coding guidelines= =0D +//=0D +typedef struct sbi_scratch SBI_SCRATCH;=0D +typedef struct sbi_platform SBI_PLATFORM;=0D +=0D +#endif=0D diff --git a/UefiCpuPkg/Include/RISC-V/OpensbiTypes.h b/UefiCpuPkg/Include/= RISC-V/OpensbiTypes.h new file mode 100644 index 0000000000..918cf686fc --- /dev/null +++ b/UefiCpuPkg/Include/RISC-V/OpensbiTypes.h @@ -0,0 +1,82 @@ +/** @file=0D + RISC-V OpenSBI header file reference.=0D +=0D + Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef EDK2_SBI_TYPES_H_=0D +#define EDK2_SBI_TYPES_H_=0D +=0D +#include =0D +=0D +typedef INT8 s8;=0D +typedef UINT8 u8;=0D +typedef UINT8 uint8_t;=0D +=0D +typedef INT16 s16;=0D +typedef UINT16 u16;=0D +typedef INT16 int16_t;=0D +typedef UINT16 uint16_t;=0D +=0D +typedef INT32 s32;=0D +typedef UINT32 u32;=0D +typedef INT32 int32_t;=0D +typedef UINT32 uint32_t;=0D +=0D +typedef INT64 s64;=0D +typedef UINT64 u64;=0D +typedef INT64 int64_t;=0D +typedef UINT64 uint64_t;=0D +=0D +// PRILX is not used in EDK2 but we need to define it here because when=0D +// defining our own types, this constant is not defined but used by OpenSB= I.=0D +#define PRILX "016lx"=0D +=0D +typedef BOOLEAN bool;=0D +typedef unsigned long ulong;=0D +typedef UINT64 uintptr_t;=0D +typedef UINT64 size_t;=0D +typedef INT64 ssize_t;=0D +typedef UINT64 virtual_addr_t;=0D +typedef UINT64 virtual_size_t;=0D +typedef UINT64 physical_addr_t;=0D +typedef UINT64 physical_size_t;=0D +=0D +#define true TRUE=0D +#define false FALSE=0D +=0D +#define __packed __attribute__((packed))=0D +#define __noreturn __attribute__((noreturn))=0D +#define __aligned(x) __attribute__((aligned(x)))=0D +=0D +#if defined (__GNUC__) || defined (__clang__)=0D +#define likely(x) __builtin_expect((x), 1)=0D +#define unlikely(x) __builtin_expect((x), 0)=0D +#else=0D +#define likely(x) (x)=0D +#define unlikely(x) (x)=0D +#endif=0D +=0D +#undef offsetof=0D +#ifdef __compiler_offsetof=0D +#define offsetof(TYPE, MEMBER) __compiler_offsetof(TYPE,MEMBER)=0D +#else=0D +#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)=0D +#endif=0D +=0D +#define container_of(ptr, type, member) ({ \=0D + const typeof(((type *)0)->member) * __mptr =3D (ptr); \=0D + (type *)((char *)__mptr - offsetof(type, member)); })=0D +=0D +#define array_size(x) (sizeof(x) / sizeof((x)[0]))=0D +=0D +#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)=0D +#define ROUNDUP(a, b) ((((a)-1) / (b) + 1) * (b))=0D +#define ROUNDDOWN(a, b) ((a) / (b) * (b))=0D +=0D +/* clang-format on */=0D +=0D +#endif=0D diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.t= emplate index 9c310cf23d..32af0bd15e 100755 --- a/BaseTools/Conf/tools_def.template +++ b/BaseTools/Conf/tools_def.template @@ -1978,7 +1978,7 @@ DEFINE GCC5_RISCV_ALL_DLINK2_FLAGS =3D= -Wl,--defsym=3DPECOFF_HEADER_S DEFINE GCC5_RISCV_ALL_ASM_FLAGS =3D -c -x assembler -ima= cros $(DEST_DIR_DEBUG)/AutoGen.h=0D DEFINE GCC5_RISCV_ALL_CC_FLAGS_WARNING_DISABLE =3D -Wno-tautological-co= mpare -Wno-pointer-compare=0D =0D -DEFINE GCC5_RISCV_OPENSBI_TYPES =3D -DOPENSBI_EXTERNAL_S= BI_TYPES=3DOpensbiTypes.h=0D +DEFINE GCC5_RISCV_OPENSBI_TYPES =3D -DOPENSBI_EXTERNAL_S= BI_TYPES=3DRISC-V/OpensbiTypes.h=0D =0D DEFINE GCC5_RISCV64_ARCH =3D rv64imafdc=0D DEFINE GCC5_RISCV32_RISCV64_ASLDLINK_FLAGS =3D DEF(GCC5_RISCV_ALL_DLINK_CO= MMON) -Wl,--entry,ReferenceAcpiTable -u ReferenceAcpiTable=0D --=20 2.31.1