From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web09.4779.1648080680578717265 for ; Wed, 23 Mar 2022 17:11:48 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=iot8nzMh; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: min.m.xu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648080708; x=1679616708; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FCqOZvANca6pJ5KxZKwkieUT7JRNLVqALG/RDF436og=; b=iot8nzMhhbpFkEdSYCndXuskq++TwALhUgQbEi/5eC+H+2XSL1hIGYYL lmfEDO7EejsVXIet8tljQo/3NTEShkamIQQOQxDipgWWhO1N+srR553Up aT/lalmvbwiNgs7a4VweNSGdLUeeXgaFf1NYZFRlgC/b7zJ0WRKV/VTWa aJtWU2N0XK1OL22BAhcz2fo6JG/kkYUD3292VsfI3MSOKroJueU3y+GCs ONI8rQBGSlPKRcydqwrUUHsqdcAO/550ONrt0EYwhElhNDk3EJGYvbKpC CfaHDNtEd7ny5411nChq5tNfI0Emgz7NS86GCjyS/yFCoWEwttJwbVW4y Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10295"; a="258207339" X-IronPort-AV: E=Sophos;i="5.90,205,1643702400"; d="scan'208";a="258207339" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2022 17:11:48 -0700 X-IronPort-AV: E=Sophos;i="5.90,205,1643702400"; d="scan'208";a="649651247" Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.31.90]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2022 17:11:45 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann , Sebastien Boeuf Subject: [PATCH V10 20/47] OvmfPkg/PlatformPei: Refactor MiscInitialization Date: Thu, 24 Mar 2022 08:10:06 +0800 Message-Id: <20220324001033.1169-21-min.m.xu@intel.com> X-Mailer: git-send-email 2.29.2.windows.2 In-Reply-To: <20220324001033.1169-1-min.m.xu@intel.com> References: <20220324001033.1169-1-min.m.xu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863 In MiscInitialization Microvm looks a little weird. Other platforms call PcdSet16S to set the PcdOvmfHostBridgePciDevId with the value same as PlatformInfoHob->HostBridgeDevId. But Microvm doesn't follow this way. In switch-case 0xffff is Microvm, but set with MICROVM_PSEUDO_DEVICE_ID. So we have to add a new function ( MiscInitializationForMicrovm ) for Microvm and delete the code in MiscInitialization. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Cc: Sebastien Boeuf Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- OvmfPkg/PlatformPei/Platform.c | 46 ++++++++++++++++++++++++++-------- 1 file changed, 36 insertions(+), 10 deletions(-) diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 80eb4cc9adcd..af9e72cd7a98 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -304,6 +304,36 @@ MicrovmInitialization ( *FdtHobData = (UINTN)NewBase; } +VOID +MiscInitializationForMicrovm ( + IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + RETURN_STATUS PcdStatus; + + ASSERT (PlatformInfoHob->HostBridgeDevId == 0xffff); + + DEBUG ((DEBUG_INFO, "%a: microvm\n", __FUNCTION__)); + // + // Disable A20 Mask + // + IoOr8 (0x92, BIT1); + + // + // Build the CPU HOB with guest RAM size dependent address width and 16-bits + // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during + // S3 resume as well, so we build it unconditionally.) + // + BuildCpuHob (PlatformInfoHob->PhysMemAddressWidth, 16); + + MicrovmInitialization (); + PcdStatus = PcdSet16S ( + PcdOvmfHostBridgePciDevId, + MICROVM_PSEUDO_DEVICE_ID + ); + ASSERT_RETURN_ERROR (PcdStatus); +} + VOID MiscInitialization ( IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob @@ -349,15 +379,6 @@ MiscInitialization ( AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL); AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN; break; - case 0xffff: /* microvm */ - DEBUG ((DEBUG_INFO, "%a: microvm\n", __FUNCTION__)); - MicrovmInitialization (); - PcdStatus = PcdSet16S ( - PcdOvmfHostBridgePciDevId, - MICROVM_PSEUDO_DEVICE_ID - ); - ASSERT_RETURN_ERROR (PcdStatus); - return; case CLOUDHV_DEVICE_ID: DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor host bridge\n", __FUNCTION__)); PcdStatus = PcdSet16S ( @@ -762,7 +783,12 @@ InitializePlatform ( InstallClearCacheCallback (); AmdSevInitialize (); - MiscInitialization (&mPlatformInfoHob); + if (mPlatformInfoHob.HostBridgeDevId == 0xffff) { + MiscInitializationForMicrovm (&mPlatformInfoHob); + } else { + MiscInitialization (&mPlatformInfoHob); + } + InstallFeatureControlCallback (); return EFI_SUCCESS; -- 2.29.2.windows.2