[PATCH V2 0/8] Rework UefiCpuPkg

[PATCH V2 0/8] Rework UefiCpuPkg

[Abner Chang]

https://bugzilla.tianocore.org/show_bug.cgi?id=3860

This is the project having rework on UefiCpuPkg in order to support a variety
of processor architectures. Some modules under UefiCpuPkg are required to be
abstract for the different archs.

In V2:
- I moved two RISC-V OpenSBI header files to under
  MdePkg/Include/IndustryStandard (5/8). However I am not sure if that is proper
  having those files there.
- Fixed some CI errors.

In V1:
The first step is to classify UefiCpuPkg modules to IA32 and X64 sections in
DSC file (Patch 1/6). Move the module to Common section later if more than one
archs can leverage the same module (such as Patch 3/6 for BaseUefiCpuLib).

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Chao Li <lichao@loongson.cn>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>

Abner Chang (8):
  [RFC] UefiCpuPkg: Classify IA32/X64 modules in DSC file
  [RFC] UefiCpuPkg/Include: Add header files of RISC-V processor
    architecture
  [RFC] UefiCpuPkg/BaseUefiCpuLib: Add RISC-V RISCV64 instace
  [RFC] UefiCpuPkg/RiscVOpensbLib: Add opensbi submodule
  [RFC] MdePkg/Include: Add RISC-V OpenSBI header files
  [RFC] BaseTools/Conf: Relocate RiscVOpensbiTypes.h
  [RFC] UefiCpuPkg/Library: Add RiscVOpensbiLib
  [RFC] UefiCpuPkg: Update YAML file for RISC-V arch

 UefiCpuPkg/UefiCpuPkg.dec                     |  26 ++-
 UefiCpuPkg/UefiCpuPkg.dsc                     |  45 +++--
 .../Library/BaseUefiCpuLib/BaseUefiCpuLib.inf |   8 +-
 .../RiscVOpensbiLib/RiscVOpensbiLib.inf       |  89 ++++++++++
 .../Include/IndustryStandard/RiscVOpensbi.h   |  62 +++++++
 .../IndustryStandard/RiscVOpensbiTypes.h      |  82 +++++++++
 .../Include/IndustryStandard/RISC-V/RiscV.h   | 162 ++++++++++++++++++
 .../Include/Library/RISC-V/RiscVCpuLib.h      | 118 +++++++++++++
 UefiCpuPkg/Include/RISC-V/RiscVImpl.h         |  87 ++++++++++
 .gitmodules                                   |  45 ++---
 BaseTools/Conf/tools_def.template             |   2 +-
 MdePkg/MdePkg.ci.yaml                         |   2 +
 .../Library/BaseUefiCpuLib/BaseUefiCpuLib.uni |   5 +-
 .../Library/BaseUefiCpuLib/RISCV64/Cpu.S      | 143 ++++++++++++++++
 .../Library/RISC-V/RiscVOpensbiLib/opensbi    |   1 +
 UefiCpuPkg/UefiCpuPkg.ci.yaml                 |  60 ++++++-
 16 files changed, 888 insertions(+), 49 deletions(-)
 create mode 100644 UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf
 create mode 100644 MdePkg/Include/IndustryStandard/RiscVOpensbi.h
 create mode 100644 MdePkg/Include/IndustryStandard/RiscVOpensbiTypes.h
 create mode 100644 UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscV.h
 create mode 100644 UefiCpuPkg/Include/Library/RISC-V/RiscVCpuLib.h
 create mode 100644 UefiCpuPkg/Include/RISC-V/RiscVImpl.h
 create mode 100644 UefiCpuPkg/Library/BaseUefiCpuLib/RISCV64/Cpu.S
 create mode 160000 UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/opensbi

-- 
2.31.1

[PATCH V2 1/8] [RFC] UefiCpuPkg: Classify IA32/X64 modules in DSC file

[Abner Chang]

https://bugzilla.tianocore.org/show_bug.cgi?id=3860

This is the first step of reworking on UefiCpuPkg in order to
accommodating all processor architectures in UEfiCpuPkg.
Classify UefiCpuPkg modules to IA32 and X64 sections in DSC file.
Move the module to Common section if more than one archs can
leverage the same module. Such as the patch 3/6 for BaseUefiCpuLib.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Chao Li <lichao@loongson.cn>
---
 UefiCpuPkg/UefiCpuPkg.dsc | 34 +++++++++++++++++++++-------------
 1 file changed, 21 insertions(+), 13 deletions(-)

diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc
index a0bbde9985..6b43ff6822 100644
--- a/UefiCpuPkg/UefiCpuPkg.dsc
+++ b/UefiCpuPkg/UefiCpuPkg.dsc
@@ -2,6 +2,7 @@
 #  UefiCpuPkg Package
 #
 #  Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>
+#  Copyright (c) 2022 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -23,7 +24,7 @@
 
 !include MdePkg/MdeLibs.dsc.inc
 
-[LibraryClasses]
+[LibraryClasses.common]
   BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
   BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
   CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
@@ -31,9 +32,7 @@
   SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
   DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
   DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
-  UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
   IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
-  MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
   PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
   PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
   UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
@@ -47,48 +46,56 @@
   PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
   TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
   DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
-  LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
   ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
   SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
   SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf
   CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
   PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
   PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
-  SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.inf
-  SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
   PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
   PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
   TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+
+[LibraryClasses.IA32, LibraryClasses.X64]
+  UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
+  MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
+  LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
+  SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.inf
+  SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
   VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf
   MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf
   SmmCpuRendezvousLib|UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.inf
 
 [LibraryClasses.common.SEC]
+  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+
+[LibraryClasses.IA32.SEC, LibraryClasses.X64.SEC]
   PlatformSecLib|UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.inf
 !if $(TOOL_CHAIN_TAG) == "XCODE5"
   CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandlerLib.inf
 !else
   CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
 !endif
-  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
   PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf
-  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
 
 [LibraryClasses.common.PEIM]
   MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
   HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
   LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxPeiLib.inf
-  MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
-  RegisterCpuFeaturesLib|UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.inf
-  CpuCacheInfoLib|UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf
 
 [LibraryClasses.IA32.PEIM, LibraryClasses.X64.PEIM]
   PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf
   CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
+  MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
+  RegisterCpuFeaturesLib|UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.inf
+  CpuCacheInfoLib|UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf
 
 [LibraryClasses.common.DXE_DRIVER]
   MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
   HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+
+[LibraryClasses.IA32.DXE_DRIVER, LibraryClasses.X64.DXE_DRIVER]
   CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
   MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
   RegisterCpuFeaturesLib|UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.inf
@@ -99,6 +106,8 @@
   MmServicesTableLib|MdePkg/Library/MmServicesTableLib/MmServicesTableLib.inf
   MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf
   HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+
+[LibraryClasses.IA32.DXE_SMM_DRIVER, LibraryClasses.X64.DXE_SMM_DRIVER]
   CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
 
 [LibraryClasses.common.MM_STANDALONE]
@@ -112,7 +121,7 @@
 # Drivers/Libraries within this package
 #
 
-[Components]
+[Components.IA32, Components.X64]
   UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
   UefiCpuPkg/CpuIoPei/CpuIoPei.inf
   UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/SecPeiDxeTimerLibUefiCpu.inf
@@ -122,7 +131,6 @@
   UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf
   UefiCpuPkg/MicrocodeMeasurementDxe/MicrocodeMeasurementDxe.inf
 
-[Components.IA32, Components.X64]
   UefiCpuPkg/CpuDxe/CpuDxe.inf
   UefiCpuPkg/CpuFeatures/CpuFeaturesPei.inf {
     <LibraryClasses>
-- 
2.31.1

[PATCH V2 2/8] [RFC] UefiCpuPkg/Include: Add header files of RISC-V processor architecture

[Abner Chang]

(This is migrated from edk2-platforms:Silicon/RISC-V)

https://bugzilla.tianocore.org/show_bug.cgi?id=3860
RISC-V processor architecture definitions.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Chao Li <lichao@loongson.cn>
---
 .../Include/IndustryStandard/RISC-V/RiscV.h   | 162 ++++++++++++++++++
 UefiCpuPkg/Include/RISC-V/RiscVImpl.h         |  87 ++++++++++
 2 files changed, 249 insertions(+)
 create mode 100644 UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscV.h
 create mode 100644 UefiCpuPkg/Include/RISC-V/RiscVImpl.h

diff --git a/UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscV.h b/UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscV.h
new file mode 100644
index 0000000000..3edd1e6263
--- /dev/null
+++ b/UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscV.h
@@ -0,0 +1,162 @@
+/** @file
+  RISC-V processor architecture definitions.
+
+  Copyright (c) 2022 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISCV_INDUSTRY_STANDARD_H_
+#define RISCV_INDUSTRY_STANDARD_H_
+
+#if defined (MDE_CPU_RISCV64)
+#define RISC_V_XLEN_BITS  64
+#else
+#endif
+
+#define RISC_V_ISA_ATOMIC_EXTENSION                           (0x00000001 << 0)
+#define RISC_V_ISA_BIT_OPERATION_EXTENSION                    (0x00000001 << 1)
+#define RISC_V_ISA_COMPRESSED_EXTENSION                       (0x00000001 << 2)
+#define RISC_V_ISA_DOUBLE_PRECISION_FP_EXTENSION              (0x00000001 << 3)
+#define RISC_V_ISA_RV32E_ISA                                  (0x00000001 << 4)
+#define RISC_V_ISA_SINGLE_PRECISION_FP_EXTENSION              (0x00000001 << 5)
+#define RISC_V_ISA_ADDITIONAL_STANDARD_EXTENSION              (0x00000001 << 6)
+#define RISC_V_ISA_RESERVED_1                                 (0x00000001 << 7)
+#define RISC_V_ISA_INTEGER_ISA_EXTENSION                      (0x00000001 << 8)
+#define RISC_V_ISA_DYNAMICALLY_TRANSLATED_LANGUAGE_EXTENSION  (0x00000001 << 9)
+#define RISC_V_ISA_RESERVED_2                                 (0x00000001 << 10)
+#define RISC_V_ISA_DECIMAL_FP_EXTENSION                       (0x00000001 << 11)
+#define RISC_V_ISA_INTEGER_MUL_DIV_EXTENSION                  (0x00000001 << 12)
+#define RISC_V_ISA_USER_LEVEL_INTERRUPT_SUPPORTED             (0x00000001 << 13)
+#define RISC_V_ISA_RESERVED_3                                 (0x00000001 << 14)
+#define RISC_V_ISA_PACKED_SIMD_EXTENSION                      (0x00000001 << 15)
+#define RISC_V_ISA_QUAD_PRECISION_FP_EXTENSION                (0x00000001 << 16)
+#define RISC_V_ISA_RESERVED_4                                 (0x00000001 << 17)
+#define RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED                (0x00000001 << 18)
+#define RISC_V_ISA_TRANSATIONAL_MEMORY_EXTENSION              (0x00000001 << 19)
+#define RISC_V_ISA_USER_MODE_IMPLEMENTED                      (0x00000001 << 20)
+#define RISC_V_ISA_VECTOR_EXTENSION                           (0x00000001 << 21)
+#define RISC_V_ISA_RESERVED_5                                 (0x00000001 << 22)
+#define RISC_V_ISA_NON_STANDARD_EXTENSION                     (0x00000001 << 23)
+#define RISC_V_ISA_RESERVED_6                                 (0x00000001 << 24)
+#define RISC_V_ISA_RESERVED_7                                 (0x00000001 << 25)
+
+//
+// RISC-V CSR definitions.
+//
+//
+// Machine information
+//
+#define RISCV_CSR_MACHINE_MVENDORID  0xF11
+#define RISCV_CSR_MACHINE_MARCHID    0xF12
+#define RISCV_CSR_MACHINE_MIMPID     0xF13
+#define RISCV_CSR_MACHINE_HARRID     0xF14
+//
+// Machine Trap Setup.
+//
+#define RISCV_CSR_MACHINE_MSTATUS  0x300
+#define RISCV_CSR_MACHINE_MISA     0x301
+#define RISCV_CSR_MACHINE_MEDELEG  0x302
+#define RISCV_CSR_MACHINE_MIDELEG  0x303
+#define RISCV_CSR_MACHINE_MIE      0x304
+#define RISCV_CSR_MACHINE_MTVEC    0x305
+
+#define RISCV_TIMER_COMPARE_BITS  32
+//
+// Machine Timer and Counter.
+//
+// #define RISCV_CSR_MACHINE_MTIME         0x701
+// #define RISCV_CSR_MACHINE_MTIMEH        0x741
+//
+// Machine Trap Handling.
+//
+#define RISCV_CSR_MACHINE_MSCRATCH  0x340
+#define RISCV_CSR_MACHINE_MEPC      0x341
+#define RISCV_CSR_MACHINE_MCAUSE    0x342
+#define MACHINE_MCAUSE_EXCEPTION_   MASK 0x0f
+#define MACHINE_MCAUSE_INTERRUPT    (RISC_V_XLEN_BITS - 1)
+#define RISCV_CSR_MACHINE_MBADADDR  0x343
+#define RISCV_CSR_MACHINE_MIP       0x344
+
+//
+// Machine Protection and Translation.
+//
+#define RISCV_CSR_MACHINE_MBASE    0x380
+#define RISCV_CSR_MACHINE_MBOUND   0x381
+#define RISCV_CSR_MACHINE_MIBASE   0x382
+#define RISCV_CSR_MACHINE_MIBOUND  0x383
+#define RISCV_CSR_MACHINE_MDBASE   0x384
+#define RISCV_CSR_MACHINE_MDBOUND  0x385
+
+//
+// Supervisor mode CSR.
+//
+#define RISCV_CSR_SUPERVISOR_SSTATUS    0x100
+#define SSTATUS_SIE_BIT_POSITION        1
+#define SSTATUS_SPP_BIT_POSITION        8
+#define RISCV_CSR_SUPERVISOR_SIE        0x104
+#define RISCV_CSR_SUPERVISOR_STVEC      0x105
+#define RISCV_CSR_SUPERVISOR_SSCRATCH   0x140
+#define RISCV_CSR_SUPERVISOR_SEPC       0x141
+#define RISCV_CSR_SUPERVISOR_SCAUSE     0x142
+#define SCAUSE_USER_SOFTWARE_INT        0
+#define SCAUSE_SUPERVISOR_SOFTWARE_INT  1
+#define SCAUSE_USER_TIMER_INT           4
+#define SCAUSE_SUPERVISOR_TIMER_INT     5
+#define SCAUSE_USER_EXTERNAL_INT        8
+#define SCAUSE_SUPERVISOR_EXTERNAL_INT  9
+#define RISCV_CSR_SUPERVISOR_STVAL      0x143
+#define RISCV_CSR_SUPERVISOR_SIP        0x144
+#define RISCV_CSR_SUPERVISOR_SATP       0x180
+
+#if defined (MDE_CPU_RISCV64)
+#define RISCV_SATP_MODE_MASK          0xF000000000000000
+#define RISCV_SATP_MODE_BIT_POSITION  60
+#endif
+#define RISCV_SATP_MODE_OFF   0
+#define RISCV_SATP_MODE_SV32  1
+#define RISCV_SATP_MODE_SV39  8
+#define RISCV_SATP_MODE_SV48  9
+#define RISCV_SATP_MODE_SV57  10
+#define RISCV_SATP_MODE_SV64  11
+
+#define SATP64_ASID_MASK  0x0FFFF00000000000
+#define SATP64_PPN_MASK   0x00000FFFFFFFFFFF
+
+#define RISCV_CAUSE_MISALIGNED_FETCH        0x0
+#define RISCV_CAUSE_FETCH_ACCESS            0x1
+#define RISCV_CAUSE_ILLEGAL_INSTRUCTION     0x2
+#define RISCV_CAUSE_BREAKPOINT              0x3
+#define RISCV_CAUSE_MISALIGNED_LOAD         0x4
+#define RISCV_CAUSE_LOAD_ACCESS             0x5
+#define RISCV_CAUSE_MISALIGNED_STORE        0x6
+#define RISCV_CAUSE_STORE_ACCESS            0x7
+#define RISCV_CAUSE_USER_ECALL              0x8
+#define RISCV_CAUSE_HYPERVISOR_ECALL        0x9
+#define RISCV_CAUSE_SUPERVISOR_ECALL        0xa
+#define RISCV_CAUSE_MACHINE_ECALL           0xb
+#define RISCV_CAUSE_FETCH_PAGE_FAULT        0xc
+#define RISCV_CAUSE_LOAD_PAGE_FAULT         0xd
+#define RISCV_CAUSE_STORE_PAGE_FAULT        0xf
+#define RISCV_CAUSE_FETCH_GUEST_PAGE_FAULT  0x14
+#define RISCV_CAUSE_LOAD_GUEST_PAGE_FAULT   0x15
+#define RISCV_CAUSE_STORE_GUEST_PAGE_FAULT  0x17
+
+//
+// Machine Read-Write Shadow of Hypervisor Read-Only Registers
+//
+#define RISCV_CSR_HTIMEW   0xB01
+#define RISCV_CSR_HTIMEHW  0xB81
+//
+// Machine Host-Target Interface (Non-Standard Berkeley Extension)
+//
+#define RISCV_CSR_MTOHOST    0x780
+#define RISCV_CSR_MFROMHOST  0x781
+
+//
+// User mode CSR
+//
+#define RISCV_CSR_CYCLE  0xc00
+#define RISCV_CSR_TIME   0xc01
+#endif
diff --git a/UefiCpuPkg/Include/RISC-V/RiscVImpl.h b/UefiCpuPkg/Include/RISC-V/RiscVImpl.h
new file mode 100644
index 0000000000..e49095de3d
--- /dev/null
+++ b/UefiCpuPkg/Include/RISC-V/RiscVImpl.h
@@ -0,0 +1,87 @@
+/** @file
+  RISC-V processor implementation definitions.
+
+  Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISCV_H_
+#define RISCV_H_
+
+#include <Uefi.h>
+#include <IndustryStandard/RISC-V/RiscV.h>
+
+#define _ASM_FUNC(Name, Section)    \
+  .global   Name                  ; \
+  .section  #Section, "ax"        ; \
+  .type     Name, %function       ; \
+  .p2align  2                     ; \
+  Name:
+
+#define ASM_FUNC(Name)  _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
+
+#if defined (MDE_CPU_RISCV64)
+typedef UINT64 RISC_V_REGS_PROTOTYPE;
+#else
+#endif
+
+//
+// Structure for 128-bit value
+//
+typedef struct {
+  UINT64    Value64_L;
+  UINT64    Value64_H;
+} RISCV_UINT128;
+
+#define RISCV_MACHINE_CONTEXT_SIZE  0x1000
+typedef struct _RISCV_MACHINE_MODE_CONTEXT RISCV_MACHINE_MODE_CONTEXT;
+
+///
+/// Exception handlers in context.
+///
+typedef struct _EXCEPTION_HANDLER_CONTEXT {
+  EFI_PHYSICAL_ADDRESS    InstAddressMisalignedHander;
+  EFI_PHYSICAL_ADDRESS    InstAccessFaultHander;
+  EFI_PHYSICAL_ADDRESS    IllegalInstHander;
+  EFI_PHYSICAL_ADDRESS    BreakpointHander;
+  EFI_PHYSICAL_ADDRESS    LoadAddrMisalignedHander;
+  EFI_PHYSICAL_ADDRESS    LoadAccessFaultHander;
+  EFI_PHYSICAL_ADDRESS    StoreAmoAddrMisalignedHander;
+  EFI_PHYSICAL_ADDRESS    StoreAmoAccessFaultHander;
+  EFI_PHYSICAL_ADDRESS    EnvCallFromUModeHander;
+  EFI_PHYSICAL_ADDRESS    EnvCallFromSModeHander;
+  EFI_PHYSICAL_ADDRESS    EnvCallFromHModeHander;
+  EFI_PHYSICAL_ADDRESS    EnvCallFromMModeHander;
+} EXCEPTION_HANDLER_CONTEXT;
+
+///
+/// Exception handlers in context.
+///
+typedef struct _INTERRUPT_HANDLER_CONTEXT {
+  EFI_PHYSICAL_ADDRESS    SoftwareIntHandler;
+  EFI_PHYSICAL_ADDRESS    TimerIntHandler;
+} INTERRUPT_HANDLER_CONTEXT;
+
+///
+/// Interrupt handlers in context.
+///
+typedef struct _TRAP_HANDLER_CONTEXT {
+  EXCEPTION_HANDLER_CONTEXT    ExceptionHandlerContext;
+  INTERRUPT_HANDLER_CONTEXT    IntHandlerContext;
+} TRAP_HANDLER_CONTEXT;
+
+///
+/// Machine mode context used for saveing hart-local context.
+///
+typedef struct _RISCV_MACHINE_MODE_CONTEXT {
+  EFI_PHYSICAL_ADDRESS    PeiService;                /// PEI service.
+  EFI_PHYSICAL_ADDRESS    MachineModeTrapHandler;    /// Machine mode trap handler.
+  EFI_PHYSICAL_ADDRESS    HypervisorModeTrapHandler; /// Hypervisor mode trap handler.
+  EFI_PHYSICAL_ADDRESS    SupervisorModeTrapHandler; /// Supervisor mode trap handler.
+  EFI_PHYSICAL_ADDRESS    UserModeTrapHandler;       /// USer mode trap handler.
+  TRAP_HANDLER_CONTEXT    MModeHandler;              /// Handler for machine mode.
+} RISCV_MACHINE_MODE_CONTEXT;
+
+#endif
-- 
2.31.1

[PATCH V2 3/8] [RFC] UefiCpuPkg/BaseUefiCpuLib: Add RISC-V RISCV64 instace

[Abner Chang]

https://bugzilla.tianocore.org/show_bug.cgi?id=3860
Add BaseUefiCpuLib instance for RISC-V RISCV64 arch.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Chao Li <lichao@loongson.cn>
---
 UefiCpuPkg/UefiCpuPkg.dec                     |  17 ++-
 UefiCpuPkg/UefiCpuPkg.dsc                     |   7 +-
 .../Library/BaseUefiCpuLib/BaseUefiCpuLib.inf |   8 +-
 .../Include/Library/RISC-V/RiscVCpuLib.h      | 118 +++++++++++++++
 .../Library/BaseUefiCpuLib/BaseUefiCpuLib.uni |   5 +-
 .../Library/BaseUefiCpuLib/RISCV64/Cpu.S      | 143 ++++++++++++++++++
 6 files changed, 286 insertions(+), 12 deletions(-)
 create mode 100644 UefiCpuPkg/Include/Library/RISC-V/RiscVCpuLib.h
 create mode 100644 UefiCpuPkg/Library/BaseUefiCpuLib/RISCV64/Cpu.S

diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index 525cde4634..613881368b 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -2,6 +2,7 @@
 # This Package provides UEFI compatible CPU modules and libraries.
 #
 # Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2022 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -18,17 +19,17 @@
   Include
 
 [LibraryClasses]
-  ##  @libraryclass  Defines some routines that are generic for IA32 family CPU
-  ##                 to be UEFI specification compliant.
-  ##
-  UefiCpuLib|Include/Library/UefiCpuLib.h
-
   ##  @libraryclass  Defines some routines that are used to register/manage/program
   ##                 CPU features.
   ##
   RegisterCpuFeaturesLib|Include/Library/RegisterCpuFeaturesLib.h
 
 [LibraryClasses.IA32, LibraryClasses.X64]
+  ##  @libraryclass  Defines some routines that are generic for IA32 family CPU
+  ##                 to be UEFI specification compliant.
+  ##
+  UefiCpuLib|Include/Library/UefiCpuLib.h
+
   ##  @libraryclass  Provides functions to manage MTRR settings on IA32 and X64 CPUs.
   ##
   MtrrLib|Include/Library/MtrrLib.h
@@ -65,6 +66,12 @@
   ## @libraryclass  Provides function for SMM CPU Rendezvous Library.
   SmmCpuRendezvousLib|Include/Library/SmmCpuRendezvousLib.h
 
+[LibraryClasses.RISCV64]
+  ##  @libraryclass  Defines some routines that are generic for RISC-V CPU
+  ##                 to be UEFI specification compliant.
+  ##
+  UefiCpuLib|Include/Library/RISC-V/RiscVCpuLib.h
+
 [Guids]
   gUefiCpuPkgTokenSpaceGuid      = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}
   gMsegSmramGuid                 = { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}
diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc
index 6b43ff6822..50c9fc294c 100644
--- a/UefiCpuPkg/UefiCpuPkg.dsc
+++ b/UefiCpuPkg/UefiCpuPkg.dsc
@@ -14,7 +14,7 @@
   PLATFORM_VERSION               = 0.90
   DSC_SPECIFICATION              = 0x00010005
   OUTPUT_DIRECTORY               = Build/UefiCpu
-  SUPPORTED_ARCHITECTURES        = IA32|X64
+  SUPPORTED_ARCHITECTURES        = IA32|X64|RISCV64
   BUILD_TARGETS                  = DEBUG|RELEASE|NOOPT
   SKUID_IDENTIFIER               = DEFAULT
 
@@ -55,9 +55,9 @@
   PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
   PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
   TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+  UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
 
 [LibraryClasses.IA32, LibraryClasses.X64]
-  UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
   MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
   LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
   SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.inf
@@ -120,6 +120,8 @@
 #
 # Drivers/Libraries within this package
 #
+[Components.common]
+  UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
 
 [Components.IA32, Components.X64]
   UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
@@ -144,7 +146,6 @@
   UefiCpuPkg/CpuIo2Smm/CpuIo2StandaloneMm.inf
   UefiCpuPkg/CpuMpPei/CpuMpPei.inf
   UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
-  UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
   UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf
   UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
   UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf
diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
index 34d3a7bb43..f43498e9b4 100644
--- a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
+++ b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
@@ -5,6 +5,7 @@
 #
 #  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
 #  Copyright (c) 2020, AMD Inc. All rights reserved.<BR>
+#  Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 ##
@@ -21,7 +22,7 @@
 #
 # The following information is for reference only and not required by the build tools.
 #
-#  VALID_ARCHITECTURES           = IA32 X64
+#  VALID_ARCHITECTURES           = IA32 X64 RISCV64
 #
 
 [Sources.IA32]
@@ -30,9 +31,12 @@
 [Sources.X64]
   X64/InitializeFpu.nasm
 
-[Sources]
+[Sources.IA32, Sources.X64]
   BaseUefiCpuLib.c
 
+[Sources.RISCV64]
+  RISCV64/Cpu.S
+
 [Packages]
   MdePkg/MdePkg.dec
   UefiCpuPkg/UefiCpuPkg.dec
diff --git a/UefiCpuPkg/Include/Library/RISC-V/RiscVCpuLib.h b/UefiCpuPkg/Include/Library/RISC-V/RiscVCpuLib.h
new file mode 100644
index 0000000000..610456d0be
--- /dev/null
+++ b/UefiCpuPkg/Include/Library/RISC-V/RiscVCpuLib.h
@@ -0,0 +1,118 @@
+/** @file
+  RISC-V CPU library definitions.
+
+  Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef RISCV_CPU_LIB_H_
+#define RISCV_CPU_LIB_H_
+
+#include "RiscVImpl.h"
+
+/**
+  RISCV_TRAP_HANDLER
+**/
+typedef
+VOID
+(EFIAPI *RISCV_TRAP_HANDLER)(
+  VOID
+  );
+
+VOID
+RiscVSetMachineScratch (
+  RISCV_MACHINE_MODE_CONTEXT  *RiscvContext
+  );
+
+UINT32
+RiscVGetMachineScratch (
+  VOID
+  );
+
+UINT32
+RiscVGetMachineTrapCause (
+  VOID
+  );
+
+UINT64
+RiscVReadMachineTimer (
+  VOID
+  );
+
+UINT64
+RiscVReadMachineTimerInterface (
+  VOID
+  );
+
+VOID
+  RiscVSetMachineTimerCmp (UINT64);
+
+UINT64
+RiscVReadMachineTimerCmp (
+  VOID
+  );
+
+UINT64
+RiscVReadMachineInterruptEnable (
+  VOID
+  );
+
+UINT64
+RiscVReadMachineInterruptPending (
+  VOID
+  );
+
+UINT64
+RiscVReadMachineStatus (
+  VOID
+  );
+
+VOID
+  RiscVWriteMachineStatus (UINT64);
+
+UINT64
+RiscVReadMachineTrapVector (
+  VOID
+  );
+
+UINT64
+RiscVReadMachineIsa (
+  VOID
+  );
+
+UINT64
+RiscVReadMachineVendorId (
+  VOID
+  );
+
+UINT64
+RiscVReadMachineArchitectureId (
+  VOID
+  );
+
+UINT64
+RiscVReadMachineImplementId (
+  VOID
+  );
+
+VOID
+  RiscVSetSupervisorAddressTranslationRegister (UINT64);
+
+VOID
+  RiscVSetSupervisorScratch (UINT64);
+
+UINT64
+RiscVGetSupervisorScratch (
+  VOID
+  );
+
+VOID
+  RiscVSetSupervisorStvec (UINT64);
+
+UINT64
+RiscVGetSupervisorStvec (
+  VOID
+  );
+
+#endif
diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni
index 83c96cea67..a94bbef53e 100644
--- a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni
+++ b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni
@@ -4,13 +4,14 @@
 // The library routines are UEFI specification compliant.
 //
 // Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+// Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 //
 // SPDX-License-Identifier: BSD-2-Clause-Patent
 //
 // **/
 
 
-#string STR_MODULE_ABSTRACT             #language en-US "Defines generic routines for IA32 family CPUs."
+#string STR_MODULE_ABSTRACT             #language en-US "Base CPU library."
 
-#string STR_MODULE_DESCRIPTION          #language en-US "The library routines comply with the UEFI Specification."
+#string STR_MODULE_DESCRIPTION          #language en-US "Base CPU library provides generic routines for specific CPU architecture."
 
diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/RISCV64/Cpu.S b/UefiCpuPkg/Library/BaseUefiCpuLib/RISCV64/Cpu.S
new file mode 100644
index 0000000000..5bc31744db
--- /dev/null
+++ b/UefiCpuPkg/Library/BaseUefiCpuLib/RISCV64/Cpu.S
@@ -0,0 +1,143 @@
+//------------------------------------------------------------------------------
+//
+// RISC-V CPU functions.
+//
+// Copyright (c) 2022 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+#include <Base.h>
+#include <RISC-V/RiscVImpl.h>
+
+.data
+
+.text
+.align 3
+
+//
+// Set machine mode scratch.
+// @param a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT.
+//
+ASM_FUNC (RiscVSetMachineScratch)
+    csrrw a1, RISCV_CSR_MACHINE_MSCRATCH, a0
+    ret
+
+//
+// Get machine mode scratch.
+// @retval a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT.
+//
+ASM_FUNC (RiscVGetMachineScratch)
+    csrrs a0, RISCV_CSR_MACHINE_MSCRATCH, 0
+    ret
+
+//
+// Get machine trap cause CSR.
+//
+ASM_FUNC (RiscVGetMachineTrapCause)
+    csrrs a0, RISCV_CSR_MACHINE_MCAUSE, 0
+    ret
+
+//
+// Get machine interrupt enable
+//
+ASM_FUNC (RiscVReadMachineInterruptEnable)
+    csrr a0, RISCV_CSR_MACHINE_MIE
+    ret
+
+//
+// Get machine interrupt pending
+//
+ASM_FUNC (RiscVReadMachineInterruptPending)
+    csrr a0, RISCV_CSR_MACHINE_MIP
+    ret
+
+//
+// Get machine status
+//
+ASM_FUNC (RiscVReadMachineStatus)
+    csrr a0, RISCV_CSR_MACHINE_MSTATUS
+    ret
+
+//
+// Set machine status
+//
+ASM_FUNC (RiscVWriteMachineStatus)
+    csrw RISCV_CSR_MACHINE_MSTATUS, a0
+    ret
+
+//
+// Get machine trap vector
+//
+ASM_FUNC (RiscVReadMachineTrapVector)
+    csrr a0, RISCV_CSR_MACHINE_MTVEC
+    ret
+
+//
+// Read machine ISA
+//
+ASM_FUNC (RiscVReadMachineIsa)
+    csrr a0, RISCV_CSR_MACHINE_MISA
+    ret
+
+//
+// Read machine vendor ID
+//
+ASM_FUNC (RiscVReadMachineVendorId)
+    csrr a0, RISCV_CSR_MACHINE_MVENDORID
+    ret
+
+//
+// Read machine architecture ID
+//
+ASM_FUNC (RiscVReadMachineArchitectureId)
+    csrr a0, RISCV_CSR_MACHINE_MARCHID
+    ret
+
+//
+// Read machine implementation ID
+//
+ASM_FUNC (RiscVReadMachineImplementId)
+    csrr a0, RISCV_CSR_MACHINE_MIMPID
+    ret
+
+//
+// Set Supervisor mode scratch.
+// @param a0 : Value set to Supervisor mode scratch
+//
+ASM_FUNC (RiscVSetSupervisorScratch)
+    csrrw a1, RISCV_CSR_SUPERVISOR_SSCRATCH, a0
+    ret
+
+//
+// Get Supervisor mode scratch.
+// @retval a0 : Value in Supervisor mode scratch
+//
+ASM_FUNC (RiscVGetSupervisorScratch)
+    csrr a0, RISCV_CSR_SUPERVISOR_SSCRATCH
+    ret
+
+//
+// Set Supervisor mode trap vector.
+// @param a0 : Value set to Supervisor mode trap vector
+//
+ASM_FUNC (RiscVSetSupervisorStvec)
+    csrrw a1, RISCV_CSR_SUPERVISOR_STVEC, a0
+    ret
+
+//
+// Get Supervisor mode scratch.
+// @retval a0 : Value in Supervisor mode trap vector
+//
+ASM_FUNC (RiscVGetSupervisorStvec)
+    csrr a0, RISCV_CSR_SUPERVISOR_STVEC
+    ret
+
+//
+// Set Supervisor Address Translation and
+// Protection Register.
+//
+ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister)
+    csrw  RISCV_CSR_SUPERVISOR_SATP, a0
+    ret
+
-- 
2.31.1

[PATCH V2 4/8] [RFC] UefiCpuPkg/RiscVOpensbLib: Add opensbi submodule

[Abner Chang]

https://bugzilla.tianocore.org/show_bug.cgi?id=3860

(This is migrated from edk2-platforms:Silicon/RISC-V)
Add RISC-V opensbi as the submoudle under UefiCpuPkg/Library/RISC-V

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Chao Li <lichao@loongson.cn>
---
 .gitmodules                                   | 45 ++++++++++---------
 .../Library/RISC-V/RiscVOpensbiLib/opensbi    |  1 +
 2 files changed, 25 insertions(+), 21 deletions(-)
 create mode 160000 UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/opensbi

diff --git a/.gitmodules b/.gitmodules
index b845c9ee3f..dd68dbfc82 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,22 +1,25 @@
-[submodule "CryptoPkg/Library/OpensslLib/openssl"]
-	path = CryptoPkg/Library/OpensslLib/openssl
-	url = https://github.com/openssl/openssl
-[submodule "SoftFloat"]
-	path = ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3
-	url = https://github.com/ucb-bar/berkeley-softfloat-3.git
-[submodule "UnitTestFrameworkPkg/Library/CmockaLib/cmocka"]
-	path = UnitTestFrameworkPkg/Library/CmockaLib/cmocka
-	url = https://github.com/tianocore/edk2-cmocka.git
-[submodule "MdeModulePkg/Universal/RegularExpressionDxe/oniguruma"]
-	path = MdeModulePkg/Universal/RegularExpressionDxe/oniguruma
-	url = https://github.com/kkos/oniguruma
-[submodule "MdeModulePkg/Library/BrotliCustomDecompressLib/brotli"]
-	path = MdeModulePkg/Library/BrotliCustomDecompressLib/brotli
-	url = https://github.com/google/brotli
-[submodule "BaseTools/Source/C/BrotliCompress/brotli"]
-	path = BaseTools/Source/C/BrotliCompress/brotli
-	url = https://github.com/google/brotli
+[submodule "CryptoPkg/Library/OpensslLib/openssl"]
+	path = CryptoPkg/Library/OpensslLib/openssl
+	url = https://github.com/openssl/openssl
+[submodule "SoftFloat"]
+	path = ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3
+	url = https://github.com/ucb-bar/berkeley-softfloat-3.git
+[submodule "UnitTestFrameworkPkg/Library/CmockaLib/cmocka"]
+	path = UnitTestFrameworkPkg/Library/CmockaLib/cmocka
+	url = https://github.com/tianocore/edk2-cmocka.git
+[submodule "MdeModulePkg/Universal/RegularExpressionDxe/oniguruma"]
+	path = MdeModulePkg/Universal/RegularExpressionDxe/oniguruma
+	url = https://github.com/kkos/oniguruma
+[submodule "MdeModulePkg/Library/BrotliCustomDecompressLib/brotli"]
+	path = MdeModulePkg/Library/BrotliCustomDecompressLib/brotli
+	url = https://github.com/google/brotli
+[submodule "BaseTools/Source/C/BrotliCompress/brotli"]
+	path = BaseTools/Source/C/BrotliCompress/brotli
+	url = https://github.com/google/brotli
 	ignore = untracked
-[submodule "RedfishPkg/Library/JsonLib/jansson"]
-	path = RedfishPkg/Library/JsonLib/jansson
-	url = https://github.com/akheron/jansson
+[submodule "RedfishPkg/Library/JsonLib/jansson"]
+	path = RedfishPkg/Library/JsonLib/jansson
+	url = https://github.com/akheron/jansson
+[submodule "UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/opensbi"]
+	path = UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/opensbi
+	url = https://github.com/riscv-software-src/opensbi
diff --git a/UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/opensbi b/UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/opensbi
new file mode 160000
index 0000000000..a731c7e369
--- /dev/null
+++ b/UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/opensbi
@@ -0,0 +1 @@
+Subproject commit a731c7e36988c3308e1978ecde491f2f6182d490
-- 
2.31.1

[PATCH V2 5/8] [RFC] MdePkg/Include: Add RISC-V OpenSBI header files

[Abner Chang]

https://bugzilla.tianocore.org/show_bug.cgi?id=3860

RiscVOpensbiTypes.h:
  The header file for building RISC-V OpenSBI library.
RiscVOpenSBI.h:
  The header file of using OpenSBI library.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
M: Liming Gao <gaoliming@byosoft.com.cn> [lgao4]
R: Zhiguang Liu <zhiguang.liu@intel.com> [LiuZhiguang001]
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Chao Li <lichao@loongson.cn>
---
 .../Include/IndustryStandard/RiscVOpensbi.h   | 62 ++++++++++++++
 .../IndustryStandard/RiscVOpensbiTypes.h      | 82 +++++++++++++++++++
 MdePkg/MdePkg.ci.yaml                         |  2 +
 3 files changed, 146 insertions(+)
 create mode 100644 MdePkg/Include/IndustryStandard/RiscVOpensbi.h
 create mode 100644 MdePkg/Include/IndustryStandard/RiscVOpensbiTypes.h

diff --git a/MdePkg/Include/IndustryStandard/RiscVOpensbi.h b/MdePkg/Include/IndustryStandard/RiscVOpensbi.h
new file mode 100644
index 0000000000..4c9186f212
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/RiscVOpensbi.h
@@ -0,0 +1,62 @@
+/** @file
+  SBI inline function calls.
+
+  Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef EDK2_RISC_V_SBI_H_
+#define EDK2_RISC_V_SBI_H_
+
+#include <RiscVImpl.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_atomic.h>
+#include <sbi/sbi_ecall_interface.h>
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_types.h>
+#include <sbi/sbi_hartmask.h>
+
+#define RISC_V_MAX_HART_SUPPORTED  SBI_HARTMASK_MAX_BITS
+
+typedef
+VOID
+(EFIAPI *RISCV_HART_SWITCH_MODE)(
+  IN  UINTN   FuncArg0,
+  IN  UINTN   FuncArg1,
+  IN  UINTN   NextAddr,
+  IN  UINTN   NextMode,
+  IN  BOOLEAN NextVirt
+  );
+
+//
+// Keep the structure member in 64-bit alignment.
+//
+typedef struct {
+  UINT64                    IsaExtensionSupported; // The ISA extension this core supported.
+  RISCV_UINT128             MachineVendorId;       // Machine vendor ID
+  RISCV_UINT128             MachineArchId;         // Machine Architecture ID
+  RISCV_UINT128             MachineImplId;         // Machine Implementation ID
+  RISCV_HART_SWITCH_MODE    HartSwitchMode;        // OpenSBI's function to switch the mode of a hart
+} EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC;
+#define FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE  (64 * 8) // This is the size of EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC
+                                                      // structure. Referred by both C code and assembly code.
+
+typedef struct {
+  UINT64                                      BootHartId;
+  VOID                                        *PeiServiceTable;    // PEI Service table
+  UINT64                                      FlattenedDeviceTree; // Pointer to Flattened Device tree
+  UINT64                                      SecPeiHandOffData;   // This is EFI_SEC_PEI_HAND_OFF passed to PEI Core.
+  EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC    *HartSpecific[RISC_V_MAX_HART_SUPPORTED];
+} EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT;
+
+//
+// Typedefs of OpenSBI type to make them conform to EDK2 coding guidelines
+//
+typedef struct sbi_scratch   SBI_SCRATCH;
+typedef struct sbi_platform  SBI_PLATFORM;
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/RiscVOpensbiTypes.h b/MdePkg/Include/IndustryStandard/RiscVOpensbiTypes.h
new file mode 100644
index 0000000000..6a6a1f532d
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/RiscVOpensbiTypes.h
@@ -0,0 +1,82 @@
+/** @file
+  RISC-V OpenSBI header file reference.
+
+  Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef EDK2_RISC_V_SBI_TYPES_H_
+#define EDK2_RISC_V_SBI_TYPES_H_
+
+#include <Base.h>
+
+typedef INT8   s8;
+typedef UINT8  u8;
+typedef UINT8  uint8_t;
+
+typedef INT16   s16;
+typedef UINT16  u16;
+typedef INT16   int16_t;
+typedef UINT16  uint16_t;
+
+typedef INT32   s32;
+typedef UINT32  u32;
+typedef INT32   int32_t;
+typedef UINT32  uint32_t;
+
+typedef INT64   s64;
+typedef UINT64  u64;
+typedef INT64   int64_t;
+typedef UINT64  uint64_t;
+
+// PRILX is not used in EDK2 but we need to define it here because when
+// defining our own types, this constant is not defined but used by OpenSBI.
+#define PRILX  "016lx"
+
+typedef BOOLEAN        bool;
+typedef unsigned long  ulong;
+typedef UINT64         uintptr_t;
+typedef UINT64         size_t;
+typedef INT64          ssize_t;
+typedef UINT64         virtual_addr_t;
+typedef UINT64         virtual_size_t;
+typedef UINT64         physical_addr_t;
+typedef UINT64         physical_size_t;
+
+#define true   TRUE
+#define false  FALSE
+
+#define __packed    __attribute__((packed))
+#define __noreturn  __attribute__((noreturn))
+#define __aligned(x)  __attribute__((aligned(x)))
+
+#if defined (__GNUC__) || defined (__clang__)
+#define likely(x)    __builtin_expect((x), 1)
+#define unlikely(x)  __builtin_expect((x), 0)
+#else
+#define likely(x)    (x)
+#define unlikely(x)  (x)
+#endif
+
+#undef offsetof
+#ifdef __compiler_offsetof
+#define offsetof(TYPE, MEMBER)  __compiler_offsetof(TYPE,MEMBER)
+#else
+#define offsetof(TYPE, MEMBER)  ((size_t) &((TYPE *)0)->MEMBER)
+#endif
+
+#define container_of(ptr, type, member)  ({           \
+  const typeof(((type *)0)->member) * __mptr = (ptr); \
+  (type *)((char *)__mptr - offsetof(type, member)); })
+
+#define array_size(x)  (sizeof(x) / sizeof((x)[0]))
+
+#define CLAMP(a, lo, hi)  MIN(MAX(a, lo), hi)
+#define ROUNDUP(a, b)     ((((a)-1) / (b) + 1) * (b))
+#define ROUNDDOWN(a, b)   ((a) / (b) * (b))
+
+/* clang-format on */
+
+#endif
diff --git a/MdePkg/MdePkg.ci.yaml b/MdePkg/MdePkg.ci.yaml
index 054233ebc7..7c05fb913f 100644
--- a/MdePkg/MdePkg.ci.yaml
+++ b/MdePkg/MdePkg.ci.yaml
@@ -50,6 +50,8 @@
             "Include/IndustryStandard/Tpm20.h",
             "Include/IndustryStandard/IoRemappingTable.h",
             "Include/IndustryStandard/UefiTcgPlatform.h",
+            "Include/IndustryStandard/RiscVOpensbi.h",
+            "Include/IndustryStandard/RiscVOpensbiTypes.h",
             "Include/Library/PcdLib.h",
             "Include/Library/SafeIntLib.h",
             "Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLib.c"
-- 
2.31.1

[PATCH V2 6/8] [RFC] BaseTools/Conf: Relocate RiscVOpensbiTypes.h

[Abner Chang]

Relocation of RiscVOpensbiTypes.h, which is under:
MdePkg/Include/IndustryStandard/

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
---
 BaseTools/Conf/tools_def.template | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.template
index 9c310cf23d..c1eea33e71 100755
--- a/BaseTools/Conf/tools_def.template
+++ b/BaseTools/Conf/tools_def.template
@@ -1978,7 +1978,7 @@ DEFINE GCC5_RISCV_ALL_DLINK2_FLAGS                = -Wl,--defsym=PECOFF_HEADER_S
 DEFINE GCC5_RISCV_ALL_ASM_FLAGS                   = -c -x assembler -imacros $(DEST_DIR_DEBUG)/AutoGen.h
 DEFINE GCC5_RISCV_ALL_CC_FLAGS_WARNING_DISABLE    = -Wno-tautological-compare -Wno-pointer-compare
 
-DEFINE GCC5_RISCV_OPENSBI_TYPES                   = -DOPENSBI_EXTERNAL_SBI_TYPES=OpensbiTypes.h
+DEFINE GCC5_RISCV_OPENSBI_TYPES                   = -DOPENSBI_EXTERNAL_SBI_TYPES=IndustryStandard/RiscVOpensbiTypes.h
 
 DEFINE GCC5_RISCV64_ARCH                   = rv64imafdc
 DEFINE GCC5_RISCV32_RISCV64_ASLDLINK_FLAGS = DEF(GCC5_RISCV_ALL_DLINK_COMMON) -Wl,--entry,ReferenceAcpiTable -u ReferenceAcpiTable
-- 
2.31.1

[PATCH V2 7/8] [RFC] UefiCpuPkg/Library: Add RiscVOpensbiLib

[Abner Chang]

https://bugzilla.tianocore.org/show_bug.cgi?id=3860
(This is migrated from edk2-platforms:Silicon/RISC-V)

EDK2 RISC-V OpenSBI library which pull in external source files under
UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/opensbi to the build process.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Chao Li <lichao@loongson.cn>
---
 UefiCpuPkg/UefiCpuPkg.dec                     |  9 +-
 UefiCpuPkg/UefiCpuPkg.dsc                     |  6 ++
 .../RiscVOpensbiLib/RiscVOpensbiLib.inf       | 89 +++++++++++++++++++
 3 files changed, 103 insertions(+), 1 deletion(-)
 create mode 100644 UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf

diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index 613881368b..f7e7142882 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -15,9 +15,16 @@
   PACKAGE_GUID                   = 2171df9b-0d39-45aa-ac37-2de190010d23
   PACKAGE_VERSION                = 0.90
 
-[Includes]
+[Includes.common]
   Include
 
+[Includes.RISCV64]
+  Include/Library
+  Library/RISC-V/RiscVOpensbiLib/opensbi         # OpenSBI header file reference ("include/sbi/...")
+  Library/RISC-V/RiscVOpensbiLib/opensbi/include # Header file reference from opensbi files, ("sbi/...")
+  Library/RISC-V/RiscVOpensbiLib/opensbi/platform/generic/include # Header file reference from opensbi files, ("sbi/...")
+
+
 [LibraryClasses]
   ##  @libraryclass  Defines some routines that are used to register/manage/program
   ##                 CPU features.
diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc
index 50c9fc294c..374e951f29 100644
--- a/UefiCpuPkg/UefiCpuPkg.dsc
+++ b/UefiCpuPkg/UefiCpuPkg.dsc
@@ -66,6 +66,9 @@
   MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf
   SmmCpuRendezvousLib|UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.inf
 
+[LibraryClasses.RISCV64]
+  RiscVOpensbiLib|UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf
+
 [LibraryClasses.common.SEC]
   HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
   MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
@@ -185,5 +188,8 @@
   UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf
   UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.inf
 
+[Components.RISCV64]
+  UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf
+
 [BuildOptions]
   *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
diff --git a/UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf b/UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf
new file mode 100644
index 0000000000..54eed050d4
--- /dev/null
+++ b/UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf
@@ -0,0 +1,89 @@
+## @file
+# RISC-V Opensbi Library Instance.
+#
+#  Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION    = 0x0001001b
+  BASE_NAME      = RiscVOpensbiLib
+  FILE_GUID      = 6EF0C812-66F6-11E9-93CE-3F5D5F0DF0A7
+  MODULE_TYPE    = BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = RiscVOpensbiLib
+
+[Sources]
+  opensbi/lib/sbi/riscv_asm.c
+  opensbi/lib/sbi/riscv_atomic.c
+  opensbi/lib/sbi/riscv_hardfp.S
+  opensbi/lib/sbi/riscv_locks.c
+  opensbi/lib/sbi/sbi_bitmap.c
+  opensbi/lib/sbi/sbi_bitops.c
+  opensbi/lib/sbi/sbi_console.c
+  opensbi/lib/sbi/sbi_domain.c
+  opensbi/lib/sbi/sbi_ecall.c
+  opensbi/lib/sbi/sbi_ecall_base.c
+  opensbi/lib/sbi/sbi_ecall_hsm.c
+  opensbi/lib/sbi/sbi_ecall_legacy.c
+  opensbi/lib/sbi/sbi_ecall_replace.c
+  opensbi/lib/sbi/sbi_ecall_vendor.c
+  opensbi/lib/sbi/sbi_emulate_csr.c
+  opensbi/lib/sbi/sbi_fifo.c
+  opensbi/lib/sbi/sbi_hart.c
+  opensbi/lib/sbi/sbi_math.c
+  opensbi/lib/sbi/sbi_hfence.S
+  opensbi/lib/sbi/sbi_hsm.c
+  opensbi/lib/sbi/sbi_illegal_insn.c
+  opensbi/lib/sbi/sbi_init.c
+  opensbi/lib/sbi/sbi_ipi.c
+  opensbi/lib/sbi/sbi_misaligned_ldst.c
+  opensbi/lib/sbi/sbi_platform.c
+  opensbi/lib/sbi/sbi_scratch.c
+  opensbi/lib/sbi/sbi_string.c
+  opensbi/lib/sbi/sbi_system.c
+  opensbi/lib/sbi/sbi_timer.c
+  opensbi/lib/sbi/sbi_tlb.c
+  opensbi/lib/sbi/sbi_trap.c
+  opensbi/lib/sbi/sbi_unpriv.c
+  opensbi/lib/sbi/sbi_expected_trap.S
+
+  opensbi/lib/utils/fdt/fdt_helper.c
+  opensbi/lib/utils/fdt/fdt_fixup.c
+  opensbi/lib/utils/fdt/fdt_domain.c
+  opensbi/lib/utils/ipi/fdt_ipi.c
+  opensbi/lib/utils/ipi/aclint_mswi.c
+  opensbi/lib/utils/ipi/fdt_ipi_mswi.c
+  opensbi/lib/utils/irqchip/fdt_irqchip.c
+  opensbi/lib/utils/irqchip/fdt_irqchip_plic.c
+  opensbi/lib/utils/irqchip/plic.c
+  opensbi/lib/utils/reset/fdt_reset.c
+  opensbi/lib/utils/reset/fdt_reset_htif.c
+  opensbi/lib/utils/reset/fdt_reset_sifive.c
+  opensbi/lib/utils/reset/fdt_reset_thead.c
+  opensbi/lib/utils/reset/fdt_reset_thead_asm.S
+  opensbi/lib/utils/serial/fdt_serial.c
+  opensbi/lib/utils/serial/fdt_serial_htif.c
+  opensbi/lib/utils/serial/fdt_serial_shakti.c
+  opensbi/lib/utils/serial/fdt_serial_sifive.c
+  opensbi/lib/utils/serial/fdt_serial_uart8250.c
+  opensbi/lib/utils/serial/fdt_serial_gaisler.c
+  opensbi/lib/utils/serial/gaisler-uart.c
+  opensbi/lib/utils/serial/shakti-uart.c
+  opensbi/lib/utils/serial/sifive-uart.c
+  opensbi/lib/utils/serial/uart8250.c
+  opensbi/lib/utils/sys/htif.c
+  opensbi/lib/utils/sys/sifive_test.c
+  opensbi/lib/utils/timer/fdt_timer.c
+  opensbi/lib/utils/timer/aclint_mtimer.c
+  opensbi/lib/utils/timer/fdt_timer_mtimer.c
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec   # For libfdt.
+  MdePkg/MdePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[BuildOptions]
+  GCC:*_*_*_PP_FLAGS = -D__ASSEMBLY__
-- 
2.31.1

[PATCH V2 8/8] [RFC] UefiCpuPkg: Update YAML file for RISC-V arch

[Abner Chang]

https://bugzilla.tianocore.org/show_bug.cgi?id=3860

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Chao Li <lichao@loongson.cn>
---
 UefiCpuPkg/UefiCpuPkg.ci.yaml | 60 +++++++++++++++++++++++++++++++++--
 1 file changed, 58 insertions(+), 2 deletions(-)

diff --git a/UefiCpuPkg/UefiCpuPkg.ci.yaml b/UefiCpuPkg/UefiCpuPkg.ci.yaml
index 6e0ab95fd8..3ac249bb46 100644
--- a/UefiCpuPkg/UefiCpuPkg.ci.yaml
+++ b/UefiCpuPkg/UefiCpuPkg.ci.yaml
@@ -3,6 +3,7 @@
 #
 # Copyright (c) Microsoft Corporation
 # Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2022 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 ##
 {
@@ -18,6 +19,10 @@
         ],
         ## Both file path and directory path are accepted.
         "IgnoreFiles": [
+            ## Below source files incorporate with open source
+            ## RISC-V OpenSBI project, in which some coding style is
+            ## not able to pass the ECC.
+            "Library/RISC-V/RiscVOpensbiLib/opensbi"
         ]
     },
     "CompilerPlugin": {
@@ -69,8 +74,59 @@
     ## options defined ci/Plugin/SpellCheck
     "SpellCheck": {
         "AuditOnly": True,           # Fails test but run in AuditOnly mode to collect log
-        "IgnoreFiles": [],           # use gitignore syntax to ignore errors in matching files
-        "ExtendWords": [],           # words to extend to the dictionary for this package
+        "IgnoreFiles": [             # use gitignore syntax to ignore errors in matching files
+            "Library/RISC-V/RiscVOpensbiLib/opensbi/**"
+        ],
+        "ExtendWords": [            # words to extend to the dictionary for this package
+            "aclint",
+            "dmdepkg",
+            "ecall",
+            "ecalls",
+            "efifstub",
+            "excep",
+            "execption",
+            "gaisler",
+            "hardfp",
+            "hfence",
+            "htimehw",
+            "htimew",
+            "impid",
+            "irqchip",
+            "keepexceptiontable",
+            "libfdt",
+            "mbase",
+            "mbound",
+            "mcause",
+            "mdbase",
+            "mdbound",
+            "memeory",
+            "mfromhost",
+            "mhartid",
+            "mibase",
+            "mibound",
+            "mideleg",
+            "mscratch",
+            "mstatus",
+            "mtimeh",
+            "mtimer",
+            "mtohost",
+            "mtvec",
+            "mvendorid",
+            "opensbi",
+            "prilx",
+            "rfence",
+            "scasue",
+            "scause",
+            "sfence",
+            "sifive",
+            "smode",
+            "sramt",
+            "sscratch",
+            "sstatus",
+            "stval",
+            "stvec",
+            "transational"
+        ],
         "IgnoreStandardPaths": [],   # Standard Plugin defined paths that should be ignore
         "AdditionalIncludePaths": [] # Additional paths to spell check (wildcards supported)
     }
-- 
2.31.1