From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web10.2345.1648192610906066933 for ; Fri, 25 Mar 2022 00:16:51 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=aUalyzAH; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=0083f32eee=abner.chang@hpe.com) Received: from pps.filterd (m0134420.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 22P7EV5Q015850; Fri, 25 Mar 2022 07:16:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : content-transfer-encoding : mime-version; s=pps0720; bh=SpiUvRumMfuh+bsoP3FzOtIynZEgmt8jRzd5s/DYHWw=; b=aUalyzAHv5v9Jly2NbIa7BAlksrPrw4qbWVLO9ZHRiT3pjx9dNhxYa35E3G1IKOwi02K z+i01ijIsmR5Mk4IvDZccPOID3iy4YFUlZLts9Z8toyCDayu6ByYi0Mp1ZB1mNz4dghC oQybp4VvUUIrZKkEs4Cayx/I5XsYy690jiZhftX1ctz4XqInQy7OEQIPyIKh6kNuUgTw KKnoQWjodDhr2nuECm4EZdSvVF6wMpXpxDkeSY87ypZ6by5y+SsWBua1efscx2WpQmen z2iRSjRwuPYbptkjLfQPCYnx0KP7jHfTFKwBKxd/42JCi2SB1+bSwEreKH3QNd5FBVMW vw== Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3f195y80n7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Mar 2022 07:16:41 +0000 Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id F2C7155; Fri, 25 Mar 2022 07:16:40 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id A675346; Fri, 25 Mar 2022 07:16:37 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Eric Dong , Ray Ni , Rahul Kumar , Sunil V L , Andrew Fish , Leif Lindholm , Michael D Kinney , Chao Li , Liming Gao , Zhiguang Liu , Bob Feng , Yuwei Chen Subject: [PATCH V2 0/8] Rework UefiCpuPkg Date: Fri, 25 Mar 2022 14:12:41 +0800 Message-Id: <20220325061249.30626-1-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 X-Proofpoint-GUID: yl9S7IeP8GKNCGqne7qHRww1h8x8LCvJ X-Proofpoint-ORIG-GUID: yl9S7IeP8GKNCGqne7qHRww1h8x8LCvJ X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.850,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-25_02,2022-03-24_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=688 impostorscore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 phishscore=0 malwarescore=0 mlxscore=0 spamscore=0 clxscore=1011 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2203250039 Content-Transfer-Encoding: 8bit https://bugzilla.tianocore.org/show_bug.cgi?id=3860 This is the project having rework on UefiCpuPkg in order to support a variety of processor architectures. Some modules under UefiCpuPkg are required to be abstract for the different archs. In V2: - I moved two RISC-V OpenSBI header files to under MdePkg/Include/IndustryStandard (5/8). However I am not sure if that is proper having those files there. - Fixed some CI errors. In V1: The first step is to classify UefiCpuPkg modules to IA32 and X64 sections in DSC file (Patch 1/6). Move the module to Common section later if more than one archs can leverage the same module (such as Patch 3/6 for BaseUefiCpuLib). Signed-off-by: Abner Chang Co-authored-by: Daniel Schaefer Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Sunil V L Cc: Andrew Fish Cc: Leif Lindholm Cc: Michael D Kinney Cc: Chao Li Cc: Liming Gao Cc: Zhiguang Liu Cc: Bob Feng Cc: Liming Gao Cc: Yuwei Chen Abner Chang (8): [RFC] UefiCpuPkg: Classify IA32/X64 modules in DSC file [RFC] UefiCpuPkg/Include: Add header files of RISC-V processor architecture [RFC] UefiCpuPkg/BaseUefiCpuLib: Add RISC-V RISCV64 instace [RFC] UefiCpuPkg/RiscVOpensbLib: Add opensbi submodule [RFC] MdePkg/Include: Add RISC-V OpenSBI header files [RFC] BaseTools/Conf: Relocate RiscVOpensbiTypes.h [RFC] UefiCpuPkg/Library: Add RiscVOpensbiLib [RFC] UefiCpuPkg: Update YAML file for RISC-V arch UefiCpuPkg/UefiCpuPkg.dec | 26 ++- UefiCpuPkg/UefiCpuPkg.dsc | 45 +++-- .../Library/BaseUefiCpuLib/BaseUefiCpuLib.inf | 8 +- .../RiscVOpensbiLib/RiscVOpensbiLib.inf | 89 ++++++++++ .../Include/IndustryStandard/RiscVOpensbi.h | 62 +++++++ .../IndustryStandard/RiscVOpensbiTypes.h | 82 +++++++++ .../Include/IndustryStandard/RISC-V/RiscV.h | 162 ++++++++++++++++++ .../Include/Library/RISC-V/RiscVCpuLib.h | 118 +++++++++++++ UefiCpuPkg/Include/RISC-V/RiscVImpl.h | 87 ++++++++++ .gitmodules | 45 ++--- BaseTools/Conf/tools_def.template | 2 +- MdePkg/MdePkg.ci.yaml | 2 + .../Library/BaseUefiCpuLib/BaseUefiCpuLib.uni | 5 +- .../Library/BaseUefiCpuLib/RISCV64/Cpu.S | 143 ++++++++++++++++ .../Library/RISC-V/RiscVOpensbiLib/opensbi | 1 + UefiCpuPkg/UefiCpuPkg.ci.yaml | 60 ++++++- 16 files changed, 888 insertions(+), 49 deletions(-) create mode 100644 UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf create mode 100644 MdePkg/Include/IndustryStandard/RiscVOpensbi.h create mode 100644 MdePkg/Include/IndustryStandard/RiscVOpensbiTypes.h create mode 100644 UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscV.h create mode 100644 UefiCpuPkg/Include/Library/RISC-V/RiscVCpuLib.h create mode 100644 UefiCpuPkg/Include/RISC-V/RiscVImpl.h create mode 100644 UefiCpuPkg/Library/BaseUefiCpuLib/RISCV64/Cpu.S create mode 160000 UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/opensbi -- 2.31.1