From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web11.2324.1648192609318382827 for ; Fri, 25 Mar 2022 00:16:49 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=hNo+3o0x; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: hpe.com, ip: 148.163.143.35, mailfrom: prvs=0083f32eee=abner.chang@hpe.com) Received: from pps.filterd (m0134424.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 22P6QqU7032494; Fri, 25 Mar 2022 07:16:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : content-transfer-encoding : mime-version; s=pps0720; bh=Lt2m6P7kxLbS7SqYV5y1ZIx6Yf2WJ5xPFjCbx3LKtQs=; b=hNo+3o0xR0Kr/3Ze2v7OsKvDzKIRMvRqI9Uqqj4nFgIpCiv0yN2/BKOdOPlu+LAWtRB3 +SzCTBSmVCzbJiAip7zfQNyejZkU8MJYdRJudo76hiE2T28rf+AfSzRiFWE1ARYM1/F8 IyLNDXKhyVdjnPGD8MV1s7Ihg/9fS2J28pmnHf/m0GvZrEnGmg/w0gg8AROPUVK22vBe YGE0Tkb6wfkLv3nfJSGpsNBrClZTjzjfyjxuLMqz68dYI4eUPZMjABWB8v3kj8BmWTZ4 +wq+DmfMxYp6USk2jZLLxswr2MTGqpPpFS9udoZoPm4yLLAzUL6GKyC3eGEq6Zbq1p2Z sA== Received: from g4t3425.houston.hpe.com (g4t3425.houston.hpe.com [15.241.140.78]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3f18fqrg97-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Mar 2022 07:16:46 +0000 Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3425.houston.hpe.com (Postfix) with ESMTP id 09047A1; Fri, 25 Mar 2022 07:16:46 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id CBCD147; Fri, 25 Mar 2022 07:16:43 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer , Sunil V L , Andrew Fish , Leif Lindholm , Michael D Kinney , Chao Li Subject: [PATCH V2 2/8] [RFC] UefiCpuPkg/Include: Add header files of RISC-V processor architecture Date: Fri, 25 Mar 2022 14:12:43 +0800 Message-Id: <20220325061249.30626-3-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220325061249.30626-1-abner.chang@hpe.com> References: <20220325061249.30626-1-abner.chang@hpe.com> X-Proofpoint-GUID: tX1NU2ChEIAuc3JccPBJo6BJcsZSHJB8 X-Proofpoint-ORIG-GUID: tX1NU2ChEIAuc3JccPBJo6BJcsZSHJB8 X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.850,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-25_02,2022-03-24_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=999 clxscore=1015 phishscore=0 impostorscore=0 bulkscore=0 adultscore=0 suspectscore=0 mlxscore=0 lowpriorityscore=0 spamscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2203250039 Content-Transfer-Encoding: quoted-printable (This is migrated from edk2-platforms:Silicon/RISC-V) https://bugzilla.tianocore.org/show_bug.cgi?id=3D3860 RISC-V processor architecture definitions. Signed-off-by: Abner Chang Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Cc: Sunil V L Cc: Andrew Fish Cc: Leif Lindholm Cc: Michael D Kinney Cc: Chao Li --- .../Include/IndustryStandard/RISC-V/RiscV.h | 162 ++++++++++++++++++ UefiCpuPkg/Include/RISC-V/RiscVImpl.h | 87 ++++++++++ 2 files changed, 249 insertions(+) create mode 100644 UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscV.h create mode 100644 UefiCpuPkg/Include/RISC-V/RiscVImpl.h diff --git a/UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscV.h b/UefiCpuPk= g/Include/IndustryStandard/RISC-V/RiscV.h new file mode 100644 index 0000000000..3edd1e6263 --- /dev/null +++ b/UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscV.h @@ -0,0 +1,162 @@ +/** @file=0D + RISC-V processor architecture definitions.=0D +=0D + Copyright (c) 2022 Hewlett Packard Enterprise Development LP. All rights= reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef RISCV_INDUSTRY_STANDARD_H_=0D +#define RISCV_INDUSTRY_STANDARD_H_=0D +=0D +#if defined (MDE_CPU_RISCV64)=0D +#define RISC_V_XLEN_BITS 64=0D +#else=0D +#endif=0D +=0D +#define RISC_V_ISA_ATOMIC_EXTENSION (0x00000001 = << 0)=0D +#define RISC_V_ISA_BIT_OPERATION_EXTENSION (0x00000001 = << 1)=0D +#define RISC_V_ISA_COMPRESSED_EXTENSION (0x00000001 = << 2)=0D +#define RISC_V_ISA_DOUBLE_PRECISION_FP_EXTENSION (0x00000001 = << 3)=0D +#define RISC_V_ISA_RV32E_ISA (0x00000001 = << 4)=0D +#define RISC_V_ISA_SINGLE_PRECISION_FP_EXTENSION (0x00000001 = << 5)=0D +#define RISC_V_ISA_ADDITIONAL_STANDARD_EXTENSION (0x00000001 = << 6)=0D +#define RISC_V_ISA_RESERVED_1 (0x00000001 = << 7)=0D +#define RISC_V_ISA_INTEGER_ISA_EXTENSION (0x00000001 = << 8)=0D +#define RISC_V_ISA_DYNAMICALLY_TRANSLATED_LANGUAGE_EXTENSION (0x00000001 = << 9)=0D +#define RISC_V_ISA_RESERVED_2 (0x00000001 = << 10)=0D +#define RISC_V_ISA_DECIMAL_FP_EXTENSION (0x00000001 = << 11)=0D +#define RISC_V_ISA_INTEGER_MUL_DIV_EXTENSION (0x00000001 = << 12)=0D +#define RISC_V_ISA_USER_LEVEL_INTERRUPT_SUPPORTED (0x00000001 = << 13)=0D +#define RISC_V_ISA_RESERVED_3 (0x00000001 = << 14)=0D +#define RISC_V_ISA_PACKED_SIMD_EXTENSION (0x00000001 = << 15)=0D +#define RISC_V_ISA_QUAD_PRECISION_FP_EXTENSION (0x00000001 = << 16)=0D +#define RISC_V_ISA_RESERVED_4 (0x00000001 = << 17)=0D +#define RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED (0x00000001 = << 18)=0D +#define RISC_V_ISA_TRANSATIONAL_MEMORY_EXTENSION (0x00000001 = << 19)=0D +#define RISC_V_ISA_USER_MODE_IMPLEMENTED (0x00000001 = << 20)=0D +#define RISC_V_ISA_VECTOR_EXTENSION (0x00000001 = << 21)=0D +#define RISC_V_ISA_RESERVED_5 (0x00000001 = << 22)=0D +#define RISC_V_ISA_NON_STANDARD_EXTENSION (0x00000001 = << 23)=0D +#define RISC_V_ISA_RESERVED_6 (0x00000001 = << 24)=0D +#define RISC_V_ISA_RESERVED_7 (0x00000001 = << 25)=0D +=0D +//=0D +// RISC-V CSR definitions.=0D +//=0D +//=0D +// Machine information=0D +//=0D +#define RISCV_CSR_MACHINE_MVENDORID 0xF11=0D +#define RISCV_CSR_MACHINE_MARCHID 0xF12=0D +#define RISCV_CSR_MACHINE_MIMPID 0xF13=0D +#define RISCV_CSR_MACHINE_HARRID 0xF14=0D +//=0D +// Machine Trap Setup.=0D +//=0D +#define RISCV_CSR_MACHINE_MSTATUS 0x300=0D +#define RISCV_CSR_MACHINE_MISA 0x301=0D +#define RISCV_CSR_MACHINE_MEDELEG 0x302=0D +#define RISCV_CSR_MACHINE_MIDELEG 0x303=0D +#define RISCV_CSR_MACHINE_MIE 0x304=0D +#define RISCV_CSR_MACHINE_MTVEC 0x305=0D +=0D +#define RISCV_TIMER_COMPARE_BITS 32=0D +//=0D +// Machine Timer and Counter.=0D +//=0D +// #define RISCV_CSR_MACHINE_MTIME 0x701=0D +// #define RISCV_CSR_MACHINE_MTIMEH 0x741=0D +//=0D +// Machine Trap Handling.=0D +//=0D +#define RISCV_CSR_MACHINE_MSCRATCH 0x340=0D +#define RISCV_CSR_MACHINE_MEPC 0x341=0D +#define RISCV_CSR_MACHINE_MCAUSE 0x342=0D +#define MACHINE_MCAUSE_EXCEPTION_ MASK 0x0f=0D +#define MACHINE_MCAUSE_INTERRUPT (RISC_V_XLEN_BITS - 1)=0D +#define RISCV_CSR_MACHINE_MBADADDR 0x343=0D +#define RISCV_CSR_MACHINE_MIP 0x344=0D +=0D +//=0D +// Machine Protection and Translation.=0D +//=0D +#define RISCV_CSR_MACHINE_MBASE 0x380=0D +#define RISCV_CSR_MACHINE_MBOUND 0x381=0D +#define RISCV_CSR_MACHINE_MIBASE 0x382=0D +#define RISCV_CSR_MACHINE_MIBOUND 0x383=0D +#define RISCV_CSR_MACHINE_MDBASE 0x384=0D +#define RISCV_CSR_MACHINE_MDBOUND 0x385=0D +=0D +//=0D +// Supervisor mode CSR.=0D +//=0D +#define RISCV_CSR_SUPERVISOR_SSTATUS 0x100=0D +#define SSTATUS_SIE_BIT_POSITION 1=0D +#define SSTATUS_SPP_BIT_POSITION 8=0D +#define RISCV_CSR_SUPERVISOR_SIE 0x104=0D +#define RISCV_CSR_SUPERVISOR_STVEC 0x105=0D +#define RISCV_CSR_SUPERVISOR_SSCRATCH 0x140=0D +#define RISCV_CSR_SUPERVISOR_SEPC 0x141=0D +#define RISCV_CSR_SUPERVISOR_SCAUSE 0x142=0D +#define SCAUSE_USER_SOFTWARE_INT 0=0D +#define SCAUSE_SUPERVISOR_SOFTWARE_INT 1=0D +#define SCAUSE_USER_TIMER_INT 4=0D +#define SCAUSE_SUPERVISOR_TIMER_INT 5=0D +#define SCAUSE_USER_EXTERNAL_INT 8=0D +#define SCAUSE_SUPERVISOR_EXTERNAL_INT 9=0D +#define RISCV_CSR_SUPERVISOR_STVAL 0x143=0D +#define RISCV_CSR_SUPERVISOR_SIP 0x144=0D +#define RISCV_CSR_SUPERVISOR_SATP 0x180=0D +=0D +#if defined (MDE_CPU_RISCV64)=0D +#define RISCV_SATP_MODE_MASK 0xF000000000000000=0D +#define RISCV_SATP_MODE_BIT_POSITION 60=0D +#endif=0D +#define RISCV_SATP_MODE_OFF 0=0D +#define RISCV_SATP_MODE_SV32 1=0D +#define RISCV_SATP_MODE_SV39 8=0D +#define RISCV_SATP_MODE_SV48 9=0D +#define RISCV_SATP_MODE_SV57 10=0D +#define RISCV_SATP_MODE_SV64 11=0D +=0D +#define SATP64_ASID_MASK 0x0FFFF00000000000=0D +#define SATP64_PPN_MASK 0x00000FFFFFFFFFFF=0D +=0D +#define RISCV_CAUSE_MISALIGNED_FETCH 0x0=0D +#define RISCV_CAUSE_FETCH_ACCESS 0x1=0D +#define RISCV_CAUSE_ILLEGAL_INSTRUCTION 0x2=0D +#define RISCV_CAUSE_BREAKPOINT 0x3=0D +#define RISCV_CAUSE_MISALIGNED_LOAD 0x4=0D +#define RISCV_CAUSE_LOAD_ACCESS 0x5=0D +#define RISCV_CAUSE_MISALIGNED_STORE 0x6=0D +#define RISCV_CAUSE_STORE_ACCESS 0x7=0D +#define RISCV_CAUSE_USER_ECALL 0x8=0D +#define RISCV_CAUSE_HYPERVISOR_ECALL 0x9=0D +#define RISCV_CAUSE_SUPERVISOR_ECALL 0xa=0D +#define RISCV_CAUSE_MACHINE_ECALL 0xb=0D +#define RISCV_CAUSE_FETCH_PAGE_FAULT 0xc=0D +#define RISCV_CAUSE_LOAD_PAGE_FAULT 0xd=0D +#define RISCV_CAUSE_STORE_PAGE_FAULT 0xf=0D +#define RISCV_CAUSE_FETCH_GUEST_PAGE_FAULT 0x14=0D +#define RISCV_CAUSE_LOAD_GUEST_PAGE_FAULT 0x15=0D +#define RISCV_CAUSE_STORE_GUEST_PAGE_FAULT 0x17=0D +=0D +//=0D +// Machine Read-Write Shadow of Hypervisor Read-Only Registers=0D +//=0D +#define RISCV_CSR_HTIMEW 0xB01=0D +#define RISCV_CSR_HTIMEHW 0xB81=0D +//=0D +// Machine Host-Target Interface (Non-Standard Berkeley Extension)=0D +//=0D +#define RISCV_CSR_MTOHOST 0x780=0D +#define RISCV_CSR_MFROMHOST 0x781=0D +=0D +//=0D +// User mode CSR=0D +//=0D +#define RISCV_CSR_CYCLE 0xc00=0D +#define RISCV_CSR_TIME 0xc01=0D +#endif=0D diff --git a/UefiCpuPkg/Include/RISC-V/RiscVImpl.h b/UefiCpuPkg/Include/RIS= C-V/RiscVImpl.h new file mode 100644 index 0000000000..e49095de3d --- /dev/null +++ b/UefiCpuPkg/Include/RISC-V/RiscVImpl.h @@ -0,0 +1,87 @@ +/** @file=0D + RISC-V processor implementation definitions.=0D +=0D + Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef RISCV_H_=0D +#define RISCV_H_=0D +=0D +#include =0D +#include =0D +=0D +#define _ASM_FUNC(Name, Section) \=0D + .global Name ; \=0D + .section #Section, "ax" ; \=0D + .type Name, %function ; \=0D + .p2align 2 ; \=0D + Name:=0D +=0D +#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)=0D +=0D +#if defined (MDE_CPU_RISCV64)=0D +typedef UINT64 RISC_V_REGS_PROTOTYPE;=0D +#else=0D +#endif=0D +=0D +//=0D +// Structure for 128-bit value=0D +//=0D +typedef struct {=0D + UINT64 Value64_L;=0D + UINT64 Value64_H;=0D +} RISCV_UINT128;=0D +=0D +#define RISCV_MACHINE_CONTEXT_SIZE 0x1000=0D +typedef struct _RISCV_MACHINE_MODE_CONTEXT RISCV_MACHINE_MODE_CONTEXT;=0D +=0D +///=0D +/// Exception handlers in context.=0D +///=0D +typedef struct _EXCEPTION_HANDLER_CONTEXT {=0D + EFI_PHYSICAL_ADDRESS InstAddressMisalignedHander;=0D + EFI_PHYSICAL_ADDRESS InstAccessFaultHander;=0D + EFI_PHYSICAL_ADDRESS IllegalInstHander;=0D + EFI_PHYSICAL_ADDRESS BreakpointHander;=0D + EFI_PHYSICAL_ADDRESS LoadAddrMisalignedHander;=0D + EFI_PHYSICAL_ADDRESS LoadAccessFaultHander;=0D + EFI_PHYSICAL_ADDRESS StoreAmoAddrMisalignedHander;=0D + EFI_PHYSICAL_ADDRESS StoreAmoAccessFaultHander;=0D + EFI_PHYSICAL_ADDRESS EnvCallFromUModeHander;=0D + EFI_PHYSICAL_ADDRESS EnvCallFromSModeHander;=0D + EFI_PHYSICAL_ADDRESS EnvCallFromHModeHander;=0D + EFI_PHYSICAL_ADDRESS EnvCallFromMModeHander;=0D +} EXCEPTION_HANDLER_CONTEXT;=0D +=0D +///=0D +/// Exception handlers in context.=0D +///=0D +typedef struct _INTERRUPT_HANDLER_CONTEXT {=0D + EFI_PHYSICAL_ADDRESS SoftwareIntHandler;=0D + EFI_PHYSICAL_ADDRESS TimerIntHandler;=0D +} INTERRUPT_HANDLER_CONTEXT;=0D +=0D +///=0D +/// Interrupt handlers in context.=0D +///=0D +typedef struct _TRAP_HANDLER_CONTEXT {=0D + EXCEPTION_HANDLER_CONTEXT ExceptionHandlerContext;=0D + INTERRUPT_HANDLER_CONTEXT IntHandlerContext;=0D +} TRAP_HANDLER_CONTEXT;=0D +=0D +///=0D +/// Machine mode context used for saveing hart-local context.=0D +///=0D +typedef struct _RISCV_MACHINE_MODE_CONTEXT {=0D + EFI_PHYSICAL_ADDRESS PeiService; /// PEI service.=0D + EFI_PHYSICAL_ADDRESS MachineModeTrapHandler; /// Machine mode trap= handler.=0D + EFI_PHYSICAL_ADDRESS HypervisorModeTrapHandler; /// Hypervisor mode t= rap handler.=0D + EFI_PHYSICAL_ADDRESS SupervisorModeTrapHandler; /// Supervisor mode t= rap handler.=0D + EFI_PHYSICAL_ADDRESS UserModeTrapHandler; /// USer mode trap ha= ndler.=0D + TRAP_HANDLER_CONTEXT MModeHandler; /// Handler for machi= ne mode.=0D +} RISCV_MACHINE_MODE_CONTEXT;=0D +=0D +#endif=0D --=20 2.31.1