From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web08.2285.1648192611126353594 for ; Fri, 25 Mar 2022 00:16:51 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=Eh+kODnZ; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=0083f32eee=abner.chang@hpe.com) Received: from pps.filterd (m0134421.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 22P6O8xg006401; Fri, 25 Mar 2022 07:16:49 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : content-transfer-encoding : mime-version; s=pps0720; bh=SOJ6ZolJ/1x+Bcm6rWl7OJ2/c9W6ECVIk6DeRp24jRA=; b=Eh+kODnZoQ3YXMK5pyX5xbYAzGolME7QKyOrBW2tZF5eN0rXXgIzg7xBb0q4IfzjfKL6 F21jLQ/S5/c6Q4iQWrPM4Ah8gC0THAJYNJGilWdc5JDdtGUWkpr2AVXsuxGT1taJuby/ 5nzu+ZR9YjEP8OxLQxepYh3pHCSurmNu2g5CZ75oCFztgvA4DRuPSEGdJXjV2T5EvHT2 m1VBlreEs3Je5JSiD30Cs8Mo9pFk0xlgU4tq/mBIG9PPsh6Bgdgjh6TQHcyyCxdfGKt4 BjTnWFuuwSLMlxQyg+MtZ8WjeApXz7zvdeHChUVMYectkMAc4o44mxI4qwLU38KF00RJ Bg== Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3f18eb0hrb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Mar 2022 07:16:49 +0000 Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id 8D2D45B; Fri, 25 Mar 2022 07:16:48 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 57B9346; Fri, 25 Mar 2022 07:16:46 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Eric Dong , Ray Ni , Rahul Kumar , Sunil V L , Andrew Fish , Leif Lindholm , Michael D Kinney , Chao Li Subject: [PATCH V2 3/8] [RFC] UefiCpuPkg/BaseUefiCpuLib: Add RISC-V RISCV64 instace Date: Fri, 25 Mar 2022 14:12:44 +0800 Message-Id: <20220325061249.30626-4-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220325061249.30626-1-abner.chang@hpe.com> References: <20220325061249.30626-1-abner.chang@hpe.com> X-Proofpoint-ORIG-GUID: HBtZnLpdNECFj7zLAsE2MZ-_fr1M5fWl X-Proofpoint-GUID: HBtZnLpdNECFj7zLAsE2MZ-_fr1M5fWl X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.850,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-25_02,2022-03-24_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 malwarescore=0 priorityscore=1501 spamscore=0 clxscore=1015 mlxscore=0 mlxlogscore=999 adultscore=0 suspectscore=0 impostorscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2203250039 Content-Transfer-Encoding: quoted-printable https://bugzilla.tianocore.org/show_bug.cgi?id=3D3860 Add BaseUefiCpuLib instance for RISC-V RISCV64 arch. Signed-off-by: Abner Chang Co-authored-by: Daniel Schaefer Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Sunil V L Cc: Andrew Fish Cc: Leif Lindholm Cc: Michael D Kinney Cc: Chao Li --- UefiCpuPkg/UefiCpuPkg.dec | 17 ++- UefiCpuPkg/UefiCpuPkg.dsc | 7 +- .../Library/BaseUefiCpuLib/BaseUefiCpuLib.inf | 8 +- .../Include/Library/RISC-V/RiscVCpuLib.h | 118 +++++++++++++++ .../Library/BaseUefiCpuLib/BaseUefiCpuLib.uni | 5 +- .../Library/BaseUefiCpuLib/RISCV64/Cpu.S | 143 ++++++++++++++++++ 6 files changed, 286 insertions(+), 12 deletions(-) create mode 100644 UefiCpuPkg/Include/Library/RISC-V/RiscVCpuLib.h create mode 100644 UefiCpuPkg/Library/BaseUefiCpuLib/RISCV64/Cpu.S diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 525cde4634..613881368b 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -2,6 +2,7 @@ # This Package provides UEFI compatible CPU modules and libraries.=0D #=0D # Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.
=0D +# Copyright (c) 2022 Hewlett Packard Enterprise Development LP. All rights= reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -18,17 +19,17 @@ Include=0D =0D [LibraryClasses]=0D - ## @libraryclass Defines some routines that are generic for IA32 famil= y CPU=0D - ## to be UEFI specification compliant.=0D - ##=0D - UefiCpuLib|Include/Library/UefiCpuLib.h=0D -=0D ## @libraryclass Defines some routines that are used to register/manag= e/program=0D ## CPU features.=0D ##=0D RegisterCpuFeaturesLib|Include/Library/RegisterCpuFeaturesLib.h=0D =0D [LibraryClasses.IA32, LibraryClasses.X64]=0D + ## @libraryclass Defines some routines that are generic for IA32 famil= y CPU=0D + ## to be UEFI specification compliant.=0D + ##=0D + UefiCpuLib|Include/Library/UefiCpuLib.h=0D +=0D ## @libraryclass Provides functions to manage MTRR settings on IA32 an= d X64 CPUs.=0D ##=0D MtrrLib|Include/Library/MtrrLib.h=0D @@ -65,6 +66,12 @@ ## @libraryclass Provides function for SMM CPU Rendezvous Library.=0D SmmCpuRendezvousLib|Include/Library/SmmCpuRendezvousLib.h=0D =0D +[LibraryClasses.RISCV64]=0D + ## @libraryclass Defines some routines that are generic for RISC-V CPU= =0D + ## to be UEFI specification compliant.=0D + ##=0D + UefiCpuLib|Include/Library/RISC-V/RiscVCpuLib.h=0D +=0D [Guids]=0D gUefiCpuPkgTokenSpaceGuid =3D { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa,= 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}=0D gMsegSmramGuid =3D { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1,= 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}=0D diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 6b43ff6822..50c9fc294c 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -14,7 +14,7 @@ PLATFORM_VERSION =3D 0.90=0D DSC_SPECIFICATION =3D 0x00010005=0D OUTPUT_DIRECTORY =3D Build/UefiCpu=0D - SUPPORTED_ARCHITECTURES =3D IA32|X64=0D + SUPPORTED_ARCHITECTURES =3D IA32|X64|RISCV64=0D BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT=0D SKUID_IDENTIFIER =3D DEFAULT=0D =0D @@ -55,9 +55,9 @@ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf=0D PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf=0D TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf=0D + UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf=0D =0D [LibraryClasses.IA32, LibraryClasses.X64]=0D - UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf=0D MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf=0D LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.in= f=0D SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCp= uPlatformHookLibNull.inf=0D @@ -120,6 +120,8 @@ #=0D # Drivers/Libraries within this package=0D #=0D +[Components.common]=0D + UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf=0D =0D [Components.IA32, Components.X64]=0D UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf=0D @@ -144,7 +146,6 @@ UefiCpuPkg/CpuIo2Smm/CpuIo2StandaloneMm.inf=0D UefiCpuPkg/CpuMpPei/CpuMpPei.inf=0D UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf=0D - UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf=0D UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf=0D UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf=0D UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf=0D diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf b/UefiCpu= Pkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf index 34d3a7bb43..f43498e9b4 100644 --- a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf +++ b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf @@ -5,6 +5,7 @@ #=0D # Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
= =0D # Copyright (c) 2020, AMD Inc. All rights reserved.
=0D +# Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D ##=0D @@ -21,7 +22,7 @@ #=0D # The following information is for reference only and not required by the = build tools.=0D #=0D -# VALID_ARCHITECTURES =3D IA32 X64=0D +# VALID_ARCHITECTURES =3D IA32 X64 RISCV64=0D #=0D =0D [Sources.IA32]=0D @@ -30,9 +31,12 @@ [Sources.X64]=0D X64/InitializeFpu.nasm=0D =0D -[Sources]=0D +[Sources.IA32, Sources.X64]=0D BaseUefiCpuLib.c=0D =0D +[Sources.RISCV64]=0D + RISCV64/Cpu.S=0D +=0D [Packages]=0D MdePkg/MdePkg.dec=0D UefiCpuPkg/UefiCpuPkg.dec=0D diff --git a/UefiCpuPkg/Include/Library/RISC-V/RiscVCpuLib.h b/UefiCpuPkg/I= nclude/Library/RISC-V/RiscVCpuLib.h new file mode 100644 index 0000000000..610456d0be --- /dev/null +++ b/UefiCpuPkg/Include/Library/RISC-V/RiscVCpuLib.h @@ -0,0 +1,118 @@ +/** @file=0D + RISC-V CPU library definitions.=0D +=0D + Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef RISCV_CPU_LIB_H_=0D +#define RISCV_CPU_LIB_H_=0D +=0D +#include "RiscVImpl.h"=0D +=0D +/**=0D + RISCV_TRAP_HANDLER=0D +**/=0D +typedef=0D +VOID=0D +(EFIAPI *RISCV_TRAP_HANDLER)(=0D + VOID=0D + );=0D +=0D +VOID=0D +RiscVSetMachineScratch (=0D + RISCV_MACHINE_MODE_CONTEXT *RiscvContext=0D + );=0D +=0D +UINT32=0D +RiscVGetMachineScratch (=0D + VOID=0D + );=0D +=0D +UINT32=0D +RiscVGetMachineTrapCause (=0D + VOID=0D + );=0D +=0D +UINT64=0D +RiscVReadMachineTimer (=0D + VOID=0D + );=0D +=0D +UINT64=0D +RiscVReadMachineTimerInterface (=0D + VOID=0D + );=0D +=0D +VOID=0D + RiscVSetMachineTimerCmp (UINT64);=0D +=0D +UINT64=0D +RiscVReadMachineTimerCmp (=0D + VOID=0D + );=0D +=0D +UINT64=0D +RiscVReadMachineInterruptEnable (=0D + VOID=0D + );=0D +=0D +UINT64=0D +RiscVReadMachineInterruptPending (=0D + VOID=0D + );=0D +=0D +UINT64=0D +RiscVReadMachineStatus (=0D + VOID=0D + );=0D +=0D +VOID=0D + RiscVWriteMachineStatus (UINT64);=0D +=0D +UINT64=0D +RiscVReadMachineTrapVector (=0D + VOID=0D + );=0D +=0D +UINT64=0D +RiscVReadMachineIsa (=0D + VOID=0D + );=0D +=0D +UINT64=0D +RiscVReadMachineVendorId (=0D + VOID=0D + );=0D +=0D +UINT64=0D +RiscVReadMachineArchitectureId (=0D + VOID=0D + );=0D +=0D +UINT64=0D +RiscVReadMachineImplementId (=0D + VOID=0D + );=0D +=0D +VOID=0D + RiscVSetSupervisorAddressTranslationRegister (UINT64);=0D +=0D +VOID=0D + RiscVSetSupervisorScratch (UINT64);=0D +=0D +UINT64=0D +RiscVGetSupervisorScratch (=0D + VOID=0D + );=0D +=0D +VOID=0D + RiscVSetSupervisorStvec (UINT64);=0D +=0D +UINT64=0D +RiscVGetSupervisorStvec (=0D + VOID=0D + );=0D +=0D +#endif=0D diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni b/UefiCpu= Pkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni index 83c96cea67..a94bbef53e 100644 --- a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni +++ b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni @@ -4,13 +4,14 @@ // The library routines are UEFI specification compliant.=0D //=0D // Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
= =0D +// Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D //=0D // SPDX-License-Identifier: BSD-2-Clause-Patent=0D //=0D // **/=0D =0D =0D -#string STR_MODULE_ABSTRACT #language en-US "Defines generic r= outines for IA32 family CPUs."=0D +#string STR_MODULE_ABSTRACT #language en-US "Base CPU library.= "=0D =0D -#string STR_MODULE_DESCRIPTION #language en-US "The library routi= nes comply with the UEFI Specification."=0D +#string STR_MODULE_DESCRIPTION #language en-US "Base CPU library = provides generic routines for specific CPU architecture."=0D =0D diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/RISCV64/Cpu.S b/UefiCpuPkg/L= ibrary/BaseUefiCpuLib/RISCV64/Cpu.S new file mode 100644 index 0000000000..5bc31744db --- /dev/null +++ b/UefiCpuPkg/Library/BaseUefiCpuLib/RISCV64/Cpu.S @@ -0,0 +1,143 @@ +//------------------------------------------------------------------------= ------=0D +//=0D +// RISC-V CPU functions.=0D +//=0D +// Copyright (c) 2022 Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +//=0D +// SPDX-License-Identifier: BSD-2-Clause-Patent=0D +//=0D +//------------------------------------------------------------------------= ------=0D +#include =0D +#include =0D +=0D +.data=0D +=0D +.text=0D +.align 3=0D +=0D +//=0D +// Set machine mode scratch.=0D +// @param a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT.=0D +//=0D +ASM_FUNC (RiscVSetMachineScratch)=0D + csrrw a1, RISCV_CSR_MACHINE_MSCRATCH, a0=0D + ret=0D +=0D +//=0D +// Get machine mode scratch.=0D +// @retval a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT.=0D +//=0D +ASM_FUNC (RiscVGetMachineScratch)=0D + csrrs a0, RISCV_CSR_MACHINE_MSCRATCH, 0=0D + ret=0D +=0D +//=0D +// Get machine trap cause CSR.=0D +//=0D +ASM_FUNC (RiscVGetMachineTrapCause)=0D + csrrs a0, RISCV_CSR_MACHINE_MCAUSE, 0=0D + ret=0D +=0D +//=0D +// Get machine interrupt enable=0D +//=0D +ASM_FUNC (RiscVReadMachineInterruptEnable)=0D + csrr a0, RISCV_CSR_MACHINE_MIE=0D + ret=0D +=0D +//=0D +// Get machine interrupt pending=0D +//=0D +ASM_FUNC (RiscVReadMachineInterruptPending)=0D + csrr a0, RISCV_CSR_MACHINE_MIP=0D + ret=0D +=0D +//=0D +// Get machine status=0D +//=0D +ASM_FUNC (RiscVReadMachineStatus)=0D + csrr a0, RISCV_CSR_MACHINE_MSTATUS=0D + ret=0D +=0D +//=0D +// Set machine status=0D +//=0D +ASM_FUNC (RiscVWriteMachineStatus)=0D + csrw RISCV_CSR_MACHINE_MSTATUS, a0=0D + ret=0D +=0D +//=0D +// Get machine trap vector=0D +//=0D +ASM_FUNC (RiscVReadMachineTrapVector)=0D + csrr a0, RISCV_CSR_MACHINE_MTVEC=0D + ret=0D +=0D +//=0D +// Read machine ISA=0D +//=0D +ASM_FUNC (RiscVReadMachineIsa)=0D + csrr a0, RISCV_CSR_MACHINE_MISA=0D + ret=0D +=0D +//=0D +// Read machine vendor ID=0D +//=0D +ASM_FUNC (RiscVReadMachineVendorId)=0D + csrr a0, RISCV_CSR_MACHINE_MVENDORID=0D + ret=0D +=0D +//=0D +// Read machine architecture ID=0D +//=0D +ASM_FUNC (RiscVReadMachineArchitectureId)=0D + csrr a0, RISCV_CSR_MACHINE_MARCHID=0D + ret=0D +=0D +//=0D +// Read machine implementation ID=0D +//=0D +ASM_FUNC (RiscVReadMachineImplementId)=0D + csrr a0, RISCV_CSR_MACHINE_MIMPID=0D + ret=0D +=0D +//=0D +// Set Supervisor mode scratch.=0D +// @param a0 : Value set to Supervisor mode scratch=0D +//=0D +ASM_FUNC (RiscVSetSupervisorScratch)=0D + csrrw a1, RISCV_CSR_SUPERVISOR_SSCRATCH, a0=0D + ret=0D +=0D +//=0D +// Get Supervisor mode scratch.=0D +// @retval a0 : Value in Supervisor mode scratch=0D +//=0D +ASM_FUNC (RiscVGetSupervisorScratch)=0D + csrr a0, RISCV_CSR_SUPERVISOR_SSCRATCH=0D + ret=0D +=0D +//=0D +// Set Supervisor mode trap vector.=0D +// @param a0 : Value set to Supervisor mode trap vector=0D +//=0D +ASM_FUNC (RiscVSetSupervisorStvec)=0D + csrrw a1, RISCV_CSR_SUPERVISOR_STVEC, a0=0D + ret=0D +=0D +//=0D +// Get Supervisor mode scratch.=0D +// @retval a0 : Value in Supervisor mode trap vector=0D +//=0D +ASM_FUNC (RiscVGetSupervisorStvec)=0D + csrr a0, RISCV_CSR_SUPERVISOR_STVEC=0D + ret=0D +=0D +//=0D +// Set Supervisor Address Translation and=0D +// Protection Register.=0D +//=0D +ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister)=0D + csrw RISCV_CSR_SUPERVISOR_SATP, a0=0D + ret=0D +=0D --=20 2.31.1