From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web11.3562.1648535835036332664 for ; Mon, 28 Mar 2022 23:37:28 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=LigilbyI; spf=pass (domain: intel.com, ip: 192.55.52.120, mailfrom: yu.pu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648535848; x=1680071848; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BYCLnINekjpS6Y3UOfMdELg479lwfk2bjDzbIgLrgME=; b=LigilbyIegwFvFJto9X5c8/QlyQazHOMlkMLk5KO8McAy6VWDqCvSLke 5SRmw0eHTGm+zE+E6QGnUOfXeybNKyCBZxkCinZq1zBjfMwsYzROiKl7l Rzc3Zts3IbujiMz3QVpV9W98w93nmI+dILhwn9aKc0FIFCQEtZS9TerI/ qykj3e44PyhjOgmL44EfJF0EvsMxn96zmshS2UhAp+e91uD5iB1LFIq+F Fmj3JzpQzWopckko+Q5qxnyOmfKl9JPVIeQC4201rrGFkA8LDPE9ual5y 6q7B6Ky7Yw0eTTUM6gJSV8g4ghvKf9VUycx38ywc0waCdjJsI1wWWY0cy A==; X-IronPort-AV: E=McAfee;i="6200,9189,10300"; a="258003889" X-IronPort-AV: E=Sophos;i="5.90,219,1643702400"; d="scan'208";a="258003889" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Mar 2022 23:37:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,219,1643702400"; d="scan'208";a="521316609" Received: from shwdeopenlab704.ccr.corp.intel.com ([10.239.182.50]) by orsmga006.jf.intel.com with ESMTP; 28 Mar 2022 23:37:25 -0700 From: Yu Pu To: devel@edk2.groups.io Cc: Yu Pu , Michael D Kinney , Liming Gao , Zhiguang Liu Subject: [PATCH v1 07/15] MdePkg: Move API and implementation from UefiCpuLib to CpuLib Date: Tue, 29 Mar 2022 14:36:55 +0800 Message-Id: <20220329063703.549-8-yu.pu@intel.com> X-Mailer: git-send-email 2.30.0.windows.2 In-Reply-To: <20220329063703.549-1-yu.pu@intel.com> References: <20220329063703.549-1-yu.pu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Step 2 to merge UefiCpuLib to CpuLib. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Signed-off-by: Yu Pu --- MdePkg/Library/BaseCpuLib/X86BaseCpuLib.c | 122 ++++++++++++++++++= ++ MdePkg/Include/Library/CpuLib.h | 65 +++++++++++ MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 6 + MdePkg/Library/BaseCpuLib/Ia32/InitializeFpu.nasm | 68 +++++++++++ MdePkg/Library/BaseCpuLib/X64/InitializeFpu.nasm | 51 ++++++++ 5 files changed, 312 insertions(+) diff --git a/MdePkg/Library/BaseCpuLib/X86BaseCpuLib.c b/MdePkg/Library/Bas= eCpuLib/X86BaseCpuLib.c new file mode 100644 index 000000000000..82c8f29137f3 --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/X86BaseCpuLib.c @@ -0,0 +1,122 @@ +/** @file=0D + This library defines some routines that are generic for IA32 family CPU.= =0D + The library routines are UEFI specification compliant.=0D + Copyright (c) 2020, AMD Inc. All rights reserved.
=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +=0D +#include =0D +#include =0D +=0D +/**=0D + Determine if the standard CPU signature is "AuthenticAMD".=0D + @retval TRUE The CPU signature matches.=0D + @retval FALSE The CPU signature does not match.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +StandardSignatureIsAuthenticAMD (=0D + VOID=0D + )=0D +{=0D + UINT32 RegEbx;=0D + UINT32 RegEcx;=0D + UINT32 RegEdx;=0D +=0D + AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);=0D + return (RegEbx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EBX &&=0D + RegEcx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_ECX &&=0D + RegEdx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EDX);=0D +}=0D +=0D +/**=0D + Return the 32bit CPU family and model value.=0D + @return CPUID[01h].EAX with Processor Type and Stepping ID cleared.=0D +**/=0D +UINT32=0D +EFIAPI=0D +GetCpuFamilyModel (=0D + VOID=0D + )=0D +{=0D + CPUID_VERSION_INFO_EAX Eax;=0D +=0D + AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, NULL, NULL);=0D +=0D + //=0D + // Mask other fields than Family and Model.=0D + //=0D + Eax.Bits.SteppingId =3D 0;=0D + Eax.Bits.ProcessorType =3D 0;=0D + Eax.Bits.Reserved1 =3D 0;=0D + Eax.Bits.Reserved2 =3D 0;=0D + return Eax.Uint32;=0D +}=0D +=0D +/**=0D + Return the CPU stepping ID.=0D + @return CPU stepping ID value in CPUID[01h].EAX.=0D +**/=0D +UINT8=0D +EFIAPI=0D +GetCpuSteppingId (=0D + VOID=0D + )=0D +{=0D + CPUID_VERSION_INFO_EAX Eax;=0D +=0D + AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, NULL, NULL);=0D +=0D + return (UINT8)Eax.Bits.SteppingId;=0D +}=0D +=0D +/**=0D + Get the physical address width supported by the processor.=0D + @param[out] ValidAddressMask Bitmask with valid address bits se= t to=0D + one; other bits are clear. Optiona= l=0D + parameter.=0D + @param[out] ValidPageBaseAddressMask Bitmask with valid page base addre= ss=0D + bits set to one; other bits are cl= ear.=0D + Optional parameter.=0D + @return The physical address width supported by the processor.=0D +**/=0D +UINT8=0D +EFIAPI=0D +GetPhysicalAddressBits (=0D + OUT UINT64 *ValidAddressMask OPTIONAL,=0D + OUT UINT64 *ValidPageBaseAddressMask OPTIONAL=0D + )=0D +{=0D + UINT32 MaxExtendedFunction;=0D + CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize;=0D + UINT64 AddressMask;=0D + UINT64 PageBaseAddressMask;=0D +=0D + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunction, NULL, NULL, NUL= L);=0D + if (MaxExtendedFunction >=3D CPUID_VIR_PHY_ADDRESS_SIZE) {=0D + AsmCpuid (=0D + CPUID_VIR_PHY_ADDRESS_SIZE,=0D + &VirPhyAddressSize.Uint32,=0D + NULL,=0D + NULL,=0D + NULL=0D + );=0D + } else {=0D + VirPhyAddressSize.Bits.PhysicalAddressBits =3D 36;=0D + }=0D +=0D + AddressMask =3D LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits= ) - 1;=0D + PageBaseAddressMask =3D AddressMask & ~(UINT64)0xFFF;=0D +=0D + if (ValidAddressMask !=3D NULL) {=0D + *ValidAddressMask =3D AddressMask;=0D + }=0D + if (ValidPageBaseAddressMask !=3D NULL) {=0D + *ValidPageBaseAddressMask =3D PageBaseAddressMask;=0D + }=0D + return (UINT8)VirPhyAddressSize.Bits.PhysicalAddressBits;=0D +}=0D diff --git a/MdePkg/Include/Library/CpuLib.h b/MdePkg/Include/Library/CpuLi= b.h index 25f6d9478c52..559de859a26e 100644 --- a/MdePkg/Include/Library/CpuLib.h +++ b/MdePkg/Include/Library/CpuLib.h @@ -41,4 +41,69 @@ CpuFlushTlb ( VOID=0D );=0D =0D +#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)=0D +=0D +/**=0D + Initializes floating point units for requirement of UEFI specification.= =0D + This function initializes floating-point control word to 0x027F (all exc= eptions=0D + masked,double-precision, round-to-nearest) and multimedia-extensions con= trol word=0D + (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush= to zero=0D + for masked underflow).=0D +**/=0D +VOID=0D +EFIAPI=0D +InitializeFloatingPointUnits (=0D + VOID=0D + );=0D +=0D +/**=0D + Determine if the standard CPU signature is "AuthenticAMD".=0D + @retval TRUE The CPU signature matches.=0D + @retval FALSE The CPU signature does not match.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +StandardSignatureIsAuthenticAMD (=0D + VOID=0D + );=0D +=0D +/**=0D + Return the 32bit CPU family and model value.=0D + @return CPUID[01h].EAX with Processor Type and Stepping ID cleared.=0D +**/=0D +UINT32=0D +EFIAPI=0D +GetCpuFamilyModel (=0D + VOID=0D + );=0D +=0D +/**=0D + Return the CPU stepping ID.=0D + @return CPU stepping ID value in CPUID[01h].EAX.=0D +**/=0D +UINT8=0D +EFIAPI=0D +GetCpuSteppingId (=0D + VOID=0D + );=0D +=0D +/**=0D + Get the physical address width supported by the processor.=0D + @param[out] ValidAddressMask Bitmask with valid address bits se= t to=0D + one; other bits are clear. Optiona= l=0D + parameter.=0D + @param[out] ValidPageBaseAddressMask Bitmask with valid page base addre= ss=0D + bits set to one; other bits are cl= ear.=0D + Optional parameter.=0D + @return The physical address width supported by the processor.=0D +**/=0D +UINT8=0D +EFIAPI=0D +GetPhysicalAddressBits (=0D + OUT UINT64 *ValidAddressMask OPTIONAL,=0D + OUT UINT64 *ValidPageBaseAddressMask OPTIONAL=0D + );=0D +=0D +#endif=0D +=0D #endif=0D diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/Base= CpuLib/BaseCpuLib.inf index 950f5229b2a4..7cdbb552c08c 100644 --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf @@ -28,6 +28,9 @@ # VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64=0D #=0D =0D +[Sources.IA32, Sources.X64]=0D + X86BaseCpuLib.c=0D +=0D [Sources.IA32]=0D Ia32/CpuSleep.c | MSFT=0D Ia32/CpuFlushTlb.c | MSFT=0D @@ -38,10 +41,13 @@ Ia32/CpuSleepGcc.c | GCC=0D Ia32/CpuFlushTlbGcc.c | GCC=0D =0D + Ia32/InitializeFpu.nasm=0D +=0D [Sources.X64]=0D X64/CpuFlushTlb.nasm=0D X64/CpuSleep.nasm=0D =0D + X64/InitializeFpu.nasm=0D =0D [Sources.EBC]=0D Ebc/CpuSleepFlushTlb.c=0D diff --git a/MdePkg/Library/BaseCpuLib/Ia32/InitializeFpu.nasm b/MdePkg/Lib= rary/BaseCpuLib/Ia32/InitializeFpu.nasm new file mode 100644 index 000000000000..5e27cc325012 --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/Ia32/InitializeFpu.nasm @@ -0,0 +1,68 @@ +;-------------------------------------------------------------------------= -----=0D +;*=0D +;* Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.=0D +;* SPDX-License-Identifier: BSD-2-Clause-Patent=0D +;*=0D +;*=0D +;-------------------------------------------------------------------------= -----=0D +=0D + SECTION .rodata=0D +=0D +;=0D +; Float control word initial value:=0D +; all exceptions masked, double-precision, round-to-nearest=0D +;=0D +mFpuControlWord: DW 0x27F=0D +;=0D +; Multimedia-extensions control word:=0D +; all exceptions masked, round-to-nearest, flush to zero for masked underf= low=0D +;=0D +mMmxControlWord: DD 0x1F80=0D +=0D + SECTION .text=0D +=0D +;=0D +; Initializes floating point units for requirement of UEFI specification.= =0D +;=0D +; This function initializes floating-point control word to 0x027F (all exc= eptions=0D +; masked,double-precision, round-to-nearest) and multimedia-extensions con= trol word=0D +; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush= to zero=0D +; for masked underflow).=0D +;=0D +global ASM_PFX(InitializeFloatingPointUnits)=0D +ASM_PFX(InitializeFloatingPointUnits):=0D +=0D + push ebx=0D +=0D + ;=0D + ; Initialize floating point units=0D + ;=0D + finit=0D + fldcw [mFpuControlWord]=0D +=0D + ;=0D + ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] =3D 1) to test=0D + ; whether the processor supports SSE instruction.=0D + ;=0D + mov eax, 1=0D + cpuid=0D + bt edx, 25=0D + jnc Done=0D +=0D + ;=0D + ; Set OSFXSR bit 9 in CR4=0D + ;=0D + mov eax, cr4=0D + or eax, BIT9=0D + mov cr4, eax=0D +=0D + ;=0D + ; The processor should support SSE instruction and we can use=0D + ; ldmxcsr instruction=0D + ;=0D + ldmxcsr [mMmxControlWord]=0D +Done:=0D + pop ebx=0D +=0D + ret=0D +=0D diff --git a/MdePkg/Library/BaseCpuLib/X64/InitializeFpu.nasm b/MdePkg/Libr= ary/BaseCpuLib/X64/InitializeFpu.nasm new file mode 100644 index 000000000000..8485b4713548 --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/X64/InitializeFpu.nasm @@ -0,0 +1,51 @@ +;-------------------------------------------------------------------------= -----=0D +;*=0D +;* Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.=0D +;* SPDX-License-Identifier: BSD-2-Clause-Patent=0D +;*=0D +;*=0D +;-------------------------------------------------------------------------= -----=0D +=0D + SECTION .rodata=0D +;=0D +; Float control word initial value:=0D +; all exceptions masked, double-extended-precision, round-to-nearest=0D +;=0D +mFpuControlWord: DW 0x37F=0D +;=0D +; Multimedia-extensions control word:=0D +; all exceptions masked, round-to-nearest, flush to zero for masked underf= low=0D +;=0D +mMmxControlWord: DD 0x1F80=0D +=0D +DEFAULT REL=0D +SECTION .text=0D +=0D +;=0D +; Initializes floating point units for requirement of UEFI specification.= =0D +;=0D +; This function initializes floating-point control word to 0x027F (all exc= eptions=0D +; masked,double-precision, round-to-nearest) and multimedia-extensions con= trol word=0D +; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush= to zero=0D +; for masked underflow).=0D +;=0D +global ASM_PFX(InitializeFloatingPointUnits)=0D +ASM_PFX(InitializeFloatingPointUnits):=0D +=0D + ;=0D + ; Initialize floating point units=0D + ;=0D + finit=0D + fldcw [mFpuControlWord]=0D +=0D + ;=0D + ; Set OSFXSR bit 9 in CR4=0D + ;=0D + mov rax, cr4=0D + or rax, BIT9=0D + mov cr4, rax=0D +=0D + ldmxcsr [mMmxControlWord]=0D +=0D + ret=0D +=0D --=20 2.30.0.windows.2