[PATCH v7 2/4] Silicon/Phytium: Added flash driver support to Phytium Silicon.

["Ling Jia" <jialing@phytium.com.cn>]

The SpiNorFlashDxe provided norflash initialization,
read-write, erase and other interfaces.

This is a set of special communication protocol for
ft2004/4 chip QSPI controller.

Signed-off-by: Ling Jia <jialing@phytium.com.cn>
Reviewed-by: leif Lindholm <leif@nuviainc.com>
---
 Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec                   |   1 +
 Platform/Phytium/DurianPkg/DurianPkg.dsc                                |  13 +
 Platform/Phytium/DurianPkg/DurianPkg.fdf                                |  24 +-
 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf   |  49 +++
 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.h     |  95 +++++
 Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashProtocol.h |  74 ++++
 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.c     | 412 ++++++++++++++++++++
 7 files changed, 658 insertions(+), 10 deletions(-)

diff --git a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec b/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
index 8427f32211..4c6c5c5f11 100644
--- a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
+++ b/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
@@ -49,3 +49,4 @@
 
 [Protocols]
   gSpiMasterProtocolGuid = { 0xdf093560, 0xf955, 0x11ea, { 0x96, 0x42, 0x43, 0x9d, 0x80, 0xdd, 0x0b, 0x7c}}
+  gSpiNorFlashProtocolGuid = { 0x00b4af42, 0xfbd0, 0x11ea, { 0x80, 0x3a, 0x27, 0xea, 0x5e, 0x65, 0xe3, 0xf6}}
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/DurianPkg/DurianPkg.dsc
index c1519070d6..cc0d418555 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.dsc
+++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc
@@ -100,6 +100,14 @@
   # Stack Size
   gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000
 
+  #
+  # SPI Flash Control Register Base Address and Size
+  #
+  gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashBase|0x0
+  gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize|0x1000000
+  gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerBase|0x28014000
+  gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerSize|0x1000
+  gPhytiumPlatformTokenSpaceGuid.PcdRtcBaseAddress|0x2800D000
   #
   # Designware PCI Root Complex
   #
@@ -255,6 +263,11 @@
   #
   Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf
 
+  #
+  # NOR Flash driver
+  #
+  Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf
+
   #
   # Usb Support
   #
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/DurianPkg/DurianPkg.fdf
index efb855c5da..5c1471d8ed 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.fdf
+++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf
@@ -83,6 +83,11 @@ READ_LOCK_STATUS   = TRUE
 
   APRIORI DXE {
     INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+    INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+    INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+    INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+    INF Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf
+    INF Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf
   }
 
   INF MdeModulePkg/Core/Dxe/DxeMain.inf
@@ -91,29 +96,28 @@ READ_LOCK_STATUS   = TRUE
   #
   # PI DXE Drivers producing Architectural Protocols (EFI Services)
   #
+  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
   INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
   INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
-  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
   INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
-  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
 
   INF Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf
-
-  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
-  INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
-
-  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
-  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
-  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
-  INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
+  INF Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf
 
   #
   # Variable services
   #
   INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
   INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
 
+  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+  INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
   INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+  INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
 
   #
   # ACPI Support
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf
new file mode 100755
index 0000000000..2173405809
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf
@@ -0,0 +1,49 @@
+#/** @file
+#  Phytium NorFlash Drivers.
+#
+#  Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001b
+  BASE_NAME                      = SpiNorFlashDxe
+  FILE_GUID                      = f37ef706-187c-48fd-9102-ddbf86f551be
+  MODULE_TYPE                    = DXE_RUNTIME_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = NorFlashPlatformEntryPoint
+
+[Sources.common]
+  SpiNorFlashDxe.c
+  SpiNorFlashDxe.h
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  IoLib
+  UefiLib
+  UefiBootServicesTableLib
+  UefiRuntimeLib
+  UefiDriverEntryPoint
+  UefiRuntimeServicesTableLib
+
+[FixedPcd]
+  gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashBase
+  gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize
+  gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerBase
+[Guids]
+  gEfiEventVirtualAddressChangeGuid
+
+[Protocols]
+  gSpiMasterProtocolGuid
+  gSpiNorFlashProtocolGuid
+
+ [Depex]
+  TRUE
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.h b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.h
new file mode 100755
index 0000000000..16981504ab
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.h
@@ -0,0 +1,95 @@
+/** @file
+  Phytium NorFlash Drivers Header.
+
+  Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SPI_NORFLASH_DXE_H_
+#define SPI_NORFLASH_DXE_H_
+
+#include <Protocol/SpiProtocol.h>
+#include <Protocol/SpiNorFlashProtocol.h>
+
+//
+//  Norflash registers
+//
+#define REG_FLASH_CAP 0x000
+#define REG_RD_CFG    0x004
+#define REG_WR_CFG    0x008
+#define REG_FLUSH_REG 0x00C
+#define REG_CMD_PORT  0x010
+#define REG_ADDR_PORT 0x014
+#define REG_HD_PORT   0x018
+#define REG_LD_PORT   0x01C
+#define REG_CS_CFG    0x020
+#define REG_WIP_CFG   0x024
+#define REG_WP_REG    0x028
+
+#define NORFLASH_SIGNATURE     SIGNATURE_32 ('F', 'T', 'S', 'F')
+#define SPI_FLASH_BASE         FixedPcdGet64 (PcdSpiFlashBase)
+#define SPI_FLASH_SIZE         FixedPcdGet64 (PcdSpiFlashSize)
+
+extern EFI_GUID gSpiMasterProtocolGuid;
+extern EFI_GUID gSpiNorFlashProtocolGuid;
+
+//
+// Platform Nor Flash Functions
+//
+EFI_STATUS
+EFIAPI
+NorFlashPlatformEraseSingleBlock (
+  IN UINTN         BlockAddress
+  );
+
+EFI_STATUS
+EFIAPI
+NorFlashPlatformErase (
+  IN UINT64        Offset,
+  IN UINT64        Length
+  );
+
+EFI_STATUS
+EFIAPI
+NorFlashPlatformRead (
+  IN UINTN          Address,
+  IN VOID           *Buffer,
+  OUT UINT32        Length
+  );
+
+EFI_STATUS
+EFIAPI
+NorFlashPlatformWrite (
+  IN UINTN         Address,
+  IN VOID          *Buffer,
+  IN UINT32        Length
+  );
+
+EFI_STATUS
+EFIAPI
+NorFlashPlatformGetDevices (
+  OUT NOR_FLASH_DEVICE_DESCRIPTION *NorFlashDevices
+  );
+
+EFI_STATUS
+EFIAPI
+NorFlashPlatformInitialization (
+  VOID
+  );
+
+EFI_STATUS
+EFIAPI
+NorFlashPlatformEntryPoint (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  );
+
+typedef struct {
+  EFI_NORFLASH_DRV_PROTOCOL FlashProtocol;
+  UINTN                   Signature;
+  EFI_HANDLE              Handle;
+} NorFlash_Device;
+
+#endif // SPI_NORFLASH_DXE_H_
diff --git a/Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashProtocol.h b/Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashProtocol.h
new file mode 100755
index 0000000000..ce1877f13a
--- /dev/null
+++ b/Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashProtocol.h
@@ -0,0 +1,74 @@
+/** @file
+  The Header of Protocol For NorFlash.
+
+  Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SPI_NORFLASH_H_
+#define SPI_NORFLASH_H_
+
+typedef struct _EFI_NORFLASH_DRV_PROTOCOL EFI_NORFLASH_DRV_PROTOCOL;
+extern EFI_GUID gSpiNorFlashProtocolGuid;
+
+typedef struct {
+  UINTN       DeviceBaseAddress;    // Start address of the Device Base Address (DBA)
+  UINTN       RegionBaseAddress;    // Start address of one single region
+  UINTN       Size;
+  UINTN       BlockSize;
+  EFI_GUID    Guid;
+} NOR_FLASH_DEVICE_DESCRIPTION;
+
+typedef
+EFI_STATUS
+(EFIAPI *NORFLASH_PLATFORM_ERASE_INTERFACE) (
+  IN UINT64        Offset,
+  IN UINT64        Length
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *NORFLASH_PLATFORM_ERASESIGLEBLOCK_INTERFACE) (
+  IN UINTN         BlockAddress
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *NORFLASH_PLATFORM_READ_INTERFACE) (
+  IN UINTN                Address,
+  IN VOID                 *Buffer,
+  OUT UINT32              Length
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *NORFLASH_PLATFORM_WRITE_INTERFACE) (
+  IN UINTN         Address,
+  IN VOID          *Buffer,
+  IN UINT32        Length
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *NORFLASH_PLATFORM_GETDEVICE_INTERFACE) (
+  OUT NOR_FLASH_DEVICE_DESCRIPTION *NorFlashDevices
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *NORFLASH_PLATFORM_INIT_INTERFACE) (
+  VOID
+  );
+
+struct _EFI_NORFLASH_DRV_PROTOCOL{
+  NORFLASH_PLATFORM_INIT_INTERFACE       Initialization;
+  NORFLASH_PLATFORM_GETDEVICE_INTERFACE  GetDevices;
+  NORFLASH_PLATFORM_ERASE_INTERFACE       Erase;
+  NORFLASH_PLATFORM_ERASESIGLEBLOCK_INTERFACE  EraseSingleBlock;
+  NORFLASH_PLATFORM_READ_INTERFACE        Read;
+  NORFLASH_PLATFORM_WRITE_INTERFACE       Write;
+};
+
+#endif // SPI_NORFLASH_H_
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.c b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.c
new file mode 100755
index 0000000000..fbeb3d1a71
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.c
@@ -0,0 +1,412 @@
+/** @file
+  Phytium NorFlash Drivers.
+
+  Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeLib.h>
+#include "SpiNorFlashDxe.h"
+
+STATIC EFI_EVENT       mSpiNorFlashVirtualAddrChangeEvent;
+STATIC UINT8           mCmdWrite;
+STATIC UINT8           mCmdErase;
+STATIC UINT8           mCmdPp;
+
+EFI_SPI_DRV_PROTOCOL *mSpiMasterProtocol;
+NorFlash_Device *mFlashInstance;
+
+NOR_FLASH_DEVICE_DESCRIPTION mNorFlashDevices = {
+    SPI_FLASH_BASE,   /* Device Base Address */
+    SPI_FLASH_BASE,   /* Region Base Address */
+    SPI_FLASH_SIZE,   /* Size */
+    SIZE_64KB,        /* Block Size */
+    {0xE7223039, 0x5836, 0x41E1, { 0xB5, 0x42, 0xD7, 0xEC, 0x73, 0x6C, 0x5E, 0x59 } }
+};
+
+
+/**
+  This function writed up to 256 bytes to flash through spi driver.
+
+  @param[in] Address             The address of the flash.
+  @param[in] Buffer              The pointer of buffer to be writed.
+  @param[in] BufferSizeInBytes   The bytes to be writed.
+
+  @retval EFI_SUCCESS           NorFlashWrite256() is executed successfully.
+
+**/
+STATIC
+EFI_STATUS
+NorFlashWrite256 (
+  IN UINTN            Address,
+  IN VOID             *Buffer,
+  IN UINT32           BufferSizeInBytes
+  )
+{
+  UINT32     Index;
+  UINT32     *TempBuffer;
+  UINT8      WriteSize;
+
+  TempBuffer = Buffer;
+  WriteSize = sizeof (UINT32);
+
+  if (BufferSizeInBytes > 256) {
+    DEBUG ((DEBUG_ERROR, "The max length is 256 bytes.\n"));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if ((BufferSizeInBytes % WriteSize) != 0) {
+    DEBUG ((DEBUG_ERROR, "The length must four bytes aligned.\n"));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if ((Address % WriteSize) != 0) {
+    DEBUG ((DEBUG_ERROR, "The address must four bytes aligned.\n"));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  mSpiMasterProtocol->SpiSetConfig (mCmdPp, 0x400000, REG_CMD_PORT);
+  mSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_LD_PORT);
+
+  mSpiMasterProtocol->SpiSetConfig (mCmdWrite, 0x000208, REG_WR_CFG);
+
+  for (Index = 0; Index < (BufferSizeInBytes / WriteSize); Index++) {
+    MmioWrite32 ((Address + (Index * WriteSize)), TempBuffer[Index]);
+  }
+
+  mSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_FLUSH_REG);
+
+  mSpiMasterProtocol->SpiSetConfig (0, 0x0, REG_WR_CFG);
+
+  return EFI_SUCCESS;
+}
+
+/**
+  This function erased a sector of flash through spi driver.
+
+  @param[in] BlockAddress  The sector address to be erased.
+
+  @retval    None.
+
+**/
+STATIC
+VOID
+NorFlashPlatformEraseSector (
+  IN  UINTN      BlockAddress
+  )
+{
+  mSpiMasterProtocol->SpiSetConfig (mCmdPp, 0x400000, REG_CMD_PORT);
+  mSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_LD_PORT);
+
+  mSpiMasterProtocol->SpiSetConfig (mCmdErase, 0x408000, REG_CMD_PORT);
+  mSpiMasterProtocol->SpiSetConfig (0, BlockAddress, REG_ADDR_PORT);
+  mSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_LD_PORT);
+
+}
+
+
+/**
+  Fixup internal data so that EFI can be call in virtual mode.
+  Call the passed in Child Notify event and convert any pointers in
+  lib to virtual mode.
+
+  @param[in] Event   The Event that is being processed.
+
+  @param[in] Context Event Context.
+
+  @retval            None.
+
+**/
+VOID
+EFIAPI
+PlatformNorFlashVirtualNotifyEvent (
+  IN EFI_EVENT            Event,
+  IN VOID                 *Context
+  )
+{
+  EfiConvertPointer (0x0, (VOID **)&(mSpiMasterProtocol->SpiGetConfig));
+  EfiConvertPointer (0x0, (VOID **)&(mSpiMasterProtocol->SpiSetConfig));
+  EfiConvertPointer (0x0, (VOID **)&(mSpiMasterProtocol));
+  EfiConvertPointer (0x0, (VOID **)&(mFlashInstance->FlashProtocol.Erase));
+  EfiConvertPointer (0x0, (VOID **)&(mFlashInstance->FlashProtocol.Read));
+  EfiConvertPointer (0x0, (VOID **)&(mFlashInstance->FlashProtocol.Write));
+  EfiConvertPointer (0x0, (VOID **)&(mFlashInstance->FlashProtocol.EraseSingleBlock));
+  EfiConvertPointer (0x0, (VOID **)&(mFlashInstance->FlashProtocol));
+  EfiConvertPointer (0x0, (VOID **)&(mFlashInstance));
+  EfiConvertPointer (0x0, (VOID **)&(mNorFlashDevices));
+
+  return;
+}
+
+
+/**
+  This function inited the flash platform.
+
+  @param None.
+
+  @retval EFI_SUCCESS           NorFlashPlatformInitialization() is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+NorFlashPlatformInitialization (
+  VOID
+  )
+{
+
+  mCmdWrite = 0x2;
+  mCmdErase = 0xD8;
+  mCmdPp = 0x6;
+
+  mSpiMasterProtocol->SpiInit();
+
+  return EFI_SUCCESS;
+}
+
+
+/**
+  This function geted the flash device information.
+
+  @param[out] NorFlashDevices    the pointer to store flash device information.
+  @param[out] Count              the number of the flash device.
+
+  @retval EFI_SUCCESS           NorFlashPlatformGetDevices() is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+NorFlashPlatformGetDevices (
+  OUT NOR_FLASH_DEVICE_DESCRIPTION   *NorFlashDevices
+  )
+{
+  *NorFlashDevices = mNorFlashDevices;
+
+  return EFI_SUCCESS;
+}
+
+
+/**
+  This function readed flash content form the specified area of flash.
+
+  @param[in] Address             The address of the flash.
+  @param[in] Buffer              The pointer of the Buffer to be stored.
+  @param[out] Length             The bytes readed form flash.
+
+  @retval EFI_SUCCESS            NorFlashPlatformRead() is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+NorFlashPlatformRead (
+  IN UINTN                Address,
+  IN VOID                 *Buffer,
+  OUT UINT32              Length
+  )
+{
+
+  CopyMem ((VOID *)Buffer, (VOID *)Address, Length);
+
+  return EFI_SUCCESS;
+}
+
+
+/**
+  This function erased one block flash content.
+
+  @param[in] BlockAddress        the BlockAddress to be erased.
+
+  @retval EFI_SUCCESS            NorFlashPlatformEraseSingleBlock() is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+NorFlashPlatformEraseSingleBlock (
+  IN UINTN      BlockAddress
+  )
+{
+
+  NorFlashPlatformEraseSector ( BlockAddress);
+
+  return EFI_SUCCESS;
+}
+
+
+/**
+  This function erased the flash content of the specified area.
+
+  @param[in] Offset              the offset of the flash.
+  @param[in] Length              length to be erased.
+
+  @retval EFI_SUCCESS            NorFlashPlatformErase() is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+NorFlashPlatformErase (
+  IN UINT64     Offset,
+  IN UINT64     Length
+  )
+{
+  EFI_STATUS     Status;
+  UINT64         Index;
+  UINT64         Count;
+
+  Status = EFI_SUCCESS;
+  if ((Length % SIZE_64KB) == 0) {
+    Count = Length / SIZE_64KB;
+    for (Index = 0; Index < Count; Index++) {
+      NorFlashPlatformEraseSingleBlock (Offset);
+      Offset += SIZE_64KB;
+    }
+  } else {
+    Status = EFI_INVALID_PARAMETER;
+  }
+
+  return Status;
+}
+
+
+/**
+  This function writed data to flash.
+
+  @param[in] Address             the address of the flash.
+
+  @param[in] Buffer              the pointer of the Buffer to be writed.
+
+  @param[in] BufferSizeInBytes   the bytes of the Buffer.
+
+  @retval EFI_SUCCESS            NorFlashPlatformWrite() is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+NorFlashPlatformWrite (
+  IN UINTN         Address,
+  IN VOID          *Buffer,
+  IN UINT32        BufferSizeInBytes
+  )
+{
+  UINT32 Index;
+  UINT32 Remainder;
+  UINT32 Quotient;
+  EFI_STATUS Status;
+  UINTN TmpAddress;
+
+  TmpAddress = Address;
+  Remainder  = BufferSizeInBytes % 256;
+  Quotient   = BufferSizeInBytes / 256;
+
+  if (BufferSizeInBytes <= 256) {
+    Status = NorFlashWrite256 (TmpAddress, Buffer, BufferSizeInBytes);
+  } else {
+    for (Index = 0; Index < Quotient; Index++) {
+        Status = NorFlashWrite256 (TmpAddress, Buffer, 256);
+        TmpAddress += 256;
+        Buffer += 256;
+    }
+
+    if (Remainder != 0) {
+      Status = NorFlashWrite256 (TmpAddress, Buffer, Remainder);
+    }
+  }
+
+  if (EFI_ERROR (Status)) {
+    ASSERT_EFI_ERROR (Status);
+  }
+
+  return EFI_SUCCESS;
+
+}
+
+
+/**
+  This function inited the flash driver protocol.
+
+  @param[in] NorFlashProtocol    A pointer to the norflash protocol struct.
+
+  @retval EFI_SUCCESS       NorFlashPlatformInitProtocol() is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+NorFlashPlatformInitProtocol (
+  IN EFI_NORFLASH_DRV_PROTOCOL *NorFlashProtocol
+  )
+{
+  NorFlashProtocol->Initialization    = NorFlashPlatformInitialization;
+  NorFlashProtocol->GetDevices        = NorFlashPlatformGetDevices;
+  NorFlashProtocol->Erase             = NorFlashPlatformErase;
+  NorFlashProtocol->EraseSingleBlock  = NorFlashPlatformEraseSingleBlock;
+  NorFlashProtocol->Read              = NorFlashPlatformRead;
+  NorFlashProtocol->Write             = NorFlashPlatformWrite;
+
+  return EFI_SUCCESS;
+}
+
+
+/**
+  This function is the entrypoint of the norflash driver.
+
+  @param[in] ImageHandle    The firmware allocated handle for the EFI image.
+
+  @param[in] SystemTable    A pointer to the EFI System Table.
+
+  @retval EFI_SUCCESS       The entry point is executed successfully.
+
+  @retval other             Some error occurs when executing this entry point.
+
+**/
+EFI_STATUS
+EFIAPI
+NorFlashPlatformEntryPoint (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  EFI_STATUS     Status;
+
+  Status = gBS->LocateProtocol (
+    &gSpiMasterProtocolGuid,
+    NULL,
+    (VOID **)&mSpiMasterProtocol
+    );
+  if (EFI_ERROR (Status)) {
+    return EFI_DEVICE_ERROR;
+  }
+
+  mFlashInstance = AllocateRuntimeZeroPool (sizeof (NorFlash_Device));
+  if (mFlashInstance == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  NorFlashPlatformInitProtocol (&mFlashInstance->FlashProtocol);
+
+  mFlashInstance->Signature = NORFLASH_SIGNATURE;
+
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &(mFlashInstance->Handle),
+                  &gSpiNorFlashProtocolGuid,
+                  &(mFlashInstance->FlashProtocol),
+                  NULL
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  //Register for the virtual address change event
+  Status = gBS->CreateEventEx (
+                  EVT_NOTIFY_SIGNAL,
+                  TPL_NOTIFY,
+                  PlatformNorFlashVirtualNotifyEvent,
+                  NULL,
+                  &gEfiEventVirtualAddressChangeGuid,
+                  &mSpiNorFlashVirtualAddrChangeEvent
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
-- 
2.25.1