From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from azure-sdnproxy-3.icoremail.net (azure-sdnproxy-3.icoremail.net [20.228.234.168]) by mx.groups.io with SMTP id smtpd.web08.8593.1649916223664874255 for ; Wed, 13 Apr 2022 23:03:46 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: phytium.com.cn, ip: 20.228.234.168, mailfrom: jialing@phytium.com.cn) Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-2 (Coremail) with SMTP id AQAAfwB3aNBduVdi7rCVAA--.4118S2; Thu, 14 Apr 2022 14:04:13 +0800 (CST) Received: from localhost.localdomain (unknown [2409:8950:e30:b22b:2796:3ef3:5bba:2229]) by mail (Coremail) with SMTP id AQAAfwD3qpswuVdisSEAAA--.705S4; Thu, 14 Apr 2022 14:03:38 +0800 (CST) From: "Ling Jia" To: devel@edk2.groups.io Cc: Leif Lindholm , Ling Jia Subject: [PATCH v7 2/4] Silicon/Phytium: Added flash driver support to Phytium Silicon. Date: Thu, 14 Apr 2022 14:03:07 +0800 Message-Id: <20220414060309.30298-3-jialing@phytium.com.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220414060309.30298-1-jialing@phytium.com.cn> References: <20220414060309.30298-1-jialing@phytium.com.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAfwD3qpswuVdisSEAAA--.705S4 X-CM-SenderInfo: xmldzxdqj61x51wl3zoofrzhdfq/ Authentication-Results: hzbj-icmmx-2; spf=neutral smtp.mail=jialing@ph ytium.com.cn; X-Coremail-Antispam: 1Uk129KBjvAXoWfCFWDCw13tr1DXrWkJrW5Wrg_yoW8uF47Jo Wxuw4SkrZ7KrWIvayjgr97Kw4xXFnavan8tr40yrZxXan7Xw43WFZrt3WUWrsxt348K3Zx K3yxXas8JFW3J3ykn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXasCq-sGcSsGvf J3UbIjqfuFe4nvWSU8nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UU UUUUUUU== Content-Transfer-Encoding: quoted-printable The SpiNorFlashDxe provided norflash initialization, read-write, erase and other interfaces. This is a set of special communication protocol for ft2004/4 chip QSPI controller. Signed-off-by: Ling Jia Reviewed-by: leif Lindholm --- Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec | = 1 + Platform/Phytium/DurianPkg/DurianPkg.dsc | = 13 + Platform/Phytium/DurianPkg/DurianPkg.fdf | = 24 +- Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf | = 49 +++ Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.h | = 95 +++++ Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashProtocol.h | = 74 ++++ Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.c | = 412 ++++++++++++++++++++ 7 files changed, 658 insertions(+), 10 deletions(-) diff --git a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec b/Silico= n/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec index 8427f32211..4c6c5c5f11 100644 --- a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec +++ b/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec @@ -49,3 +49,4 @@ =0D [Protocols]=0D gSpiMasterProtocolGuid =3D { 0xdf093560, 0xf955, 0x11ea, { 0x96, 0x42, 0= x43, 0x9d, 0x80, 0xdd, 0x0b, 0x7c}}=0D + gSpiNorFlashProtocolGuid =3D { 0x00b4af42, 0xfbd0, 0x11ea, { 0x80, 0x3a,= 0x27, 0xea, 0x5e, 0x65, 0xe3, 0xf6}}=0D diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/Du= rianPkg/DurianPkg.dsc index c1519070d6..cc0d418555 100644 --- a/Platform/Phytium/DurianPkg/DurianPkg.dsc +++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc @@ -100,6 +100,14 @@ # Stack Size=0D gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000=0D =0D + #=0D + # SPI Flash Control Register Base Address and Size=0D + #=0D + gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashBase|0x0=0D + gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize|0x1000000=0D + gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerBase|0x28014000=0D + gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerSize|0x1000=0D + gPhytiumPlatformTokenSpaceGuid.PcdRtcBaseAddress|0x2800D000=0D #=0D # Designware PCI Root Complex=0D #=0D @@ -255,6 +263,11 @@ #=0D Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf=0D =0D + #=0D + # NOR Flash driver=0D + #=0D + Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf=0D +=0D #=0D # Usb Support=0D #=0D diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/Du= rianPkg/DurianPkg.fdf index efb855c5da..5c1471d8ed 100644 --- a/Platform/Phytium/DurianPkg/DurianPkg.fdf +++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf @@ -83,6 +83,11 @@ READ_LOCK_STATUS =3D TRUE =0D APRIORI DXE {=0D INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf=0D + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf=0D + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf=0D + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf=0D + INF Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf=0D + INF Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.= inf=0D }=0D =0D INF MdeModulePkg/Core/Dxe/DxeMain.inf=0D @@ -91,29 +96,28 @@ READ_LOCK_STATUS =3D TRUE #=0D # PI DXE Drivers producing Architectural Protocols (EFI Services)=0D #=0D + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf=0D + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf=0D INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf=0D + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf=0D INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf=0D - INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf=0D INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf=0D - INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf=0D =0D INF Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf=0D -=0D - INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf=0D - INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRu= ntimeDxe.inf=0D -=0D - INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf=0D - INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf=0D - INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf=0D - INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf=0D + INF Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.in= f=0D =0D #=0D # Variable services=0D #=0D INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf=0D INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.i= nf=0D + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf=0D =0D + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf=0D + INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf=0D INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf=0D + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRu= ntimeDxe.inf=0D + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf=0D =0D #=0D # ACPI Support=0D diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlash= Dxe.inf b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe= .inf new file mode 100755 index 0000000000..2173405809 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf @@ -0,0 +1,49 @@ +#/** @file=0D +# Phytium NorFlash Drivers.=0D +#=0D +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#**/=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x0001001b=0D + BASE_NAME =3D SpiNorFlashDxe=0D + FILE_GUID =3D f37ef706-187c-48fd-9102-ddbf86f551be= =0D + MODULE_TYPE =3D DXE_RUNTIME_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D NorFlashPlatformEntryPoint=0D +=0D +[Sources.common]=0D + SpiNorFlashDxe.c=0D + SpiNorFlashDxe.h=0D +=0D +[Packages]=0D + ArmPkg/ArmPkg.dec=0D + MdePkg/MdePkg.dec=0D + Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + DebugLib=0D + IoLib=0D + UefiLib=0D + UefiBootServicesTableLib=0D + UefiRuntimeLib=0D + UefiDriverEntryPoint=0D + UefiRuntimeServicesTableLib=0D +=0D +[FixedPcd]=0D + gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashBase=0D + gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize=0D + gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerBase=0D +[Guids]=0D + gEfiEventVirtualAddressChangeGuid=0D +=0D +[Protocols]=0D + gSpiMasterProtocolGuid=0D + gSpiNorFlashProtocolGuid=0D +=0D + [Depex]=0D + TRUE=0D diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlash= Dxe.h b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.h new file mode 100755 index 0000000000..16981504ab --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.h @@ -0,0 +1,95 @@ +/** @file=0D + Phytium NorFlash Drivers Header.=0D +=0D + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef SPI_NORFLASH_DXE_H_=0D +#define SPI_NORFLASH_DXE_H_=0D +=0D +#include =0D +#include =0D +=0D +//=0D +// Norflash registers=0D +//=0D +#define REG_FLASH_CAP 0x000=0D +#define REG_RD_CFG 0x004=0D +#define REG_WR_CFG 0x008=0D +#define REG_FLUSH_REG 0x00C=0D +#define REG_CMD_PORT 0x010=0D +#define REG_ADDR_PORT 0x014=0D +#define REG_HD_PORT 0x018=0D +#define REG_LD_PORT 0x01C=0D +#define REG_CS_CFG 0x020=0D +#define REG_WIP_CFG 0x024=0D +#define REG_WP_REG 0x028=0D +=0D +#define NORFLASH_SIGNATURE SIGNATURE_32 ('F', 'T', 'S', 'F')=0D +#define SPI_FLASH_BASE FixedPcdGet64 (PcdSpiFlashBase)=0D +#define SPI_FLASH_SIZE FixedPcdGet64 (PcdSpiFlashSize)=0D +=0D +extern EFI_GUID gSpiMasterProtocolGuid;=0D +extern EFI_GUID gSpiNorFlashProtocolGuid;=0D +=0D +//=0D +// Platform Nor Flash Functions=0D +//=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformEraseSingleBlock (=0D + IN UINTN BlockAddress=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformErase (=0D + IN UINT64 Offset,=0D + IN UINT64 Length=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformRead (=0D + IN UINTN Address,=0D + IN VOID *Buffer,=0D + OUT UINT32 Length=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformWrite (=0D + IN UINTN Address,=0D + IN VOID *Buffer,=0D + IN UINT32 Length=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformGetDevices (=0D + OUT NOR_FLASH_DEVICE_DESCRIPTION *NorFlashDevices=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformInitialization (=0D + VOID=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformEntryPoint (=0D + IN EFI_HANDLE ImageHandle,=0D + IN EFI_SYSTEM_TABLE *SystemTable=0D + );=0D +=0D +typedef struct {=0D + EFI_NORFLASH_DRV_PROTOCOL FlashProtocol;=0D + UINTN Signature;=0D + EFI_HANDLE Handle;=0D +} NorFlash_Device;=0D +=0D +#endif // SPI_NORFLASH_DXE_H_=0D diff --git a/Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashP= rotocol.h b/Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashPr= otocol.h new file mode 100755 index 0000000000..ce1877f13a --- /dev/null +++ b/Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashProtocol= .h @@ -0,0 +1,74 @@ +/** @file=0D + The Header of Protocol For NorFlash.=0D +=0D + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef SPI_NORFLASH_H_=0D +#define SPI_NORFLASH_H_=0D +=0D +typedef struct _EFI_NORFLASH_DRV_PROTOCOL EFI_NORFLASH_DRV_PROTOCOL;=0D +extern EFI_GUID gSpiNorFlashProtocolGuid;=0D +=0D +typedef struct {=0D + UINTN DeviceBaseAddress; // Start address of the Device Base Ad= dress (DBA)=0D + UINTN RegionBaseAddress; // Start address of one single region= =0D + UINTN Size;=0D + UINTN BlockSize;=0D + EFI_GUID Guid;=0D +} NOR_FLASH_DEVICE_DESCRIPTION;=0D +=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *NORFLASH_PLATFORM_ERASE_INTERFACE) (=0D + IN UINT64 Offset,=0D + IN UINT64 Length=0D + );=0D +=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *NORFLASH_PLATFORM_ERASESIGLEBLOCK_INTERFACE) (=0D + IN UINTN BlockAddress=0D + );=0D +=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *NORFLASH_PLATFORM_READ_INTERFACE) (=0D + IN UINTN Address,=0D + IN VOID *Buffer,=0D + OUT UINT32 Length=0D + );=0D +=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *NORFLASH_PLATFORM_WRITE_INTERFACE) (=0D + IN UINTN Address,=0D + IN VOID *Buffer,=0D + IN UINT32 Length=0D + );=0D +=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *NORFLASH_PLATFORM_GETDEVICE_INTERFACE) (=0D + OUT NOR_FLASH_DEVICE_DESCRIPTION *NorFlashDevices=0D + );=0D +=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *NORFLASH_PLATFORM_INIT_INTERFACE) (=0D + VOID=0D + );=0D +=0D +struct _EFI_NORFLASH_DRV_PROTOCOL{=0D + NORFLASH_PLATFORM_INIT_INTERFACE Initialization;=0D + NORFLASH_PLATFORM_GETDEVICE_INTERFACE GetDevices;=0D + NORFLASH_PLATFORM_ERASE_INTERFACE Erase;=0D + NORFLASH_PLATFORM_ERASESIGLEBLOCK_INTERFACE EraseSingleBlock;=0D + NORFLASH_PLATFORM_READ_INTERFACE Read;=0D + NORFLASH_PLATFORM_WRITE_INTERFACE Write;=0D +};=0D +=0D +#endif // SPI_NORFLASH_H_=0D diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlash= Dxe.c b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.c new file mode 100755 index 0000000000..fbeb3d1a71 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.c @@ -0,0 +1,412 @@ +/** @file=0D + Phytium NorFlash Drivers.=0D +=0D + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include "SpiNorFlashDxe.h"=0D +=0D +STATIC EFI_EVENT mSpiNorFlashVirtualAddrChangeEvent;=0D +STATIC UINT8 mCmdWrite;=0D +STATIC UINT8 mCmdErase;=0D +STATIC UINT8 mCmdPp;=0D +=0D +EFI_SPI_DRV_PROTOCOL *mSpiMasterProtocol;=0D +NorFlash_Device *mFlashInstance;=0D +=0D +NOR_FLASH_DEVICE_DESCRIPTION mNorFlashDevices =3D {=0D + SPI_FLASH_BASE, /* Device Base Address */=0D + SPI_FLASH_BASE, /* Region Base Address */=0D + SPI_FLASH_SIZE, /* Size */=0D + SIZE_64KB, /* Block Size */=0D + {0xE7223039, 0x5836, 0x41E1, { 0xB5, 0x42, 0xD7, 0xEC, 0x73, 0x6C, 0x5= E, 0x59 } }=0D +};=0D +=0D +=0D +/**=0D + This function writed up to 256 bytes to flash through spi driver.=0D +=0D + @param[in] Address The address of the flash.=0D + @param[in] Buffer The pointer of buffer to be writed.=0D + @param[in] BufferSizeInBytes The bytes to be writed.=0D +=0D + @retval EFI_SUCCESS NorFlashWrite256() is executed successfull= y.=0D +=0D +**/=0D +STATIC=0D +EFI_STATUS=0D +NorFlashWrite256 (=0D + IN UINTN Address,=0D + IN VOID *Buffer,=0D + IN UINT32 BufferSizeInBytes=0D + )=0D +{=0D + UINT32 Index;=0D + UINT32 *TempBuffer;=0D + UINT8 WriteSize;=0D +=0D + TempBuffer =3D Buffer;=0D + WriteSize =3D sizeof (UINT32);=0D +=0D + if (BufferSizeInBytes > 256) {=0D + DEBUG ((DEBUG_ERROR, "The max length is 256 bytes.\n"));=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + if ((BufferSizeInBytes % WriteSize) !=3D 0) {=0D + DEBUG ((DEBUG_ERROR, "The length must four bytes aligned.\n"));=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + if ((Address % WriteSize) !=3D 0) {=0D + DEBUG ((DEBUG_ERROR, "The address must four bytes aligned.\n"));=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + mSpiMasterProtocol->SpiSetConfig (mCmdPp, 0x400000, REG_CMD_PORT);=0D + mSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_LD_PORT);=0D +=0D + mSpiMasterProtocol->SpiSetConfig (mCmdWrite, 0x000208, REG_WR_CFG);=0D +=0D + for (Index =3D 0; Index < (BufferSizeInBytes / WriteSize); Index++) {=0D + MmioWrite32 ((Address + (Index * WriteSize)), TempBuffer[Index]);=0D + }=0D +=0D + mSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_FLUSH_REG);=0D +=0D + mSpiMasterProtocol->SpiSetConfig (0, 0x0, REG_WR_CFG);=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + This function erased a sector of flash through spi driver.=0D +=0D + @param[in] BlockAddress The sector address to be erased.=0D +=0D + @retval None.=0D +=0D +**/=0D +STATIC=0D +VOID=0D +NorFlashPlatformEraseSector (=0D + IN UINTN BlockAddress=0D + )=0D +{=0D + mSpiMasterProtocol->SpiSetConfig (mCmdPp, 0x400000, REG_CMD_PORT);=0D + mSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_LD_PORT);=0D +=0D + mSpiMasterProtocol->SpiSetConfig (mCmdErase, 0x408000, REG_CMD_PORT);=0D + mSpiMasterProtocol->SpiSetConfig (0, BlockAddress, REG_ADDR_PORT);=0D + mSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_LD_PORT);=0D +=0D +}=0D +=0D +=0D +/**=0D + Fixup internal data so that EFI can be call in virtual mode.=0D + Call the passed in Child Notify event and convert any pointers in=0D + lib to virtual mode.=0D +=0D + @param[in] Event The Event that is being processed.=0D +=0D + @param[in] Context Event Context.=0D +=0D + @retval None.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +PlatformNorFlashVirtualNotifyEvent (=0D + IN EFI_EVENT Event,=0D + IN VOID *Context=0D + )=0D +{=0D + EfiConvertPointer (0x0, (VOID **)&(mSpiMasterProtocol->SpiGetConfig));=0D + EfiConvertPointer (0x0, (VOID **)&(mSpiMasterProtocol->SpiSetConfig));=0D + EfiConvertPointer (0x0, (VOID **)&(mSpiMasterProtocol));=0D + EfiConvertPointer (0x0, (VOID **)&(mFlashInstance->FlashProtocol.Erase))= ;=0D + EfiConvertPointer (0x0, (VOID **)&(mFlashInstance->FlashProtocol.Read));= =0D + EfiConvertPointer (0x0, (VOID **)&(mFlashInstance->FlashProtocol.Write))= ;=0D + EfiConvertPointer (0x0, (VOID **)&(mFlashInstance->FlashProtocol.EraseSi= ngleBlock));=0D + EfiConvertPointer (0x0, (VOID **)&(mFlashInstance->FlashProtocol));=0D + EfiConvertPointer (0x0, (VOID **)&(mFlashInstance));=0D + EfiConvertPointer (0x0, (VOID **)&(mNorFlashDevices));=0D +=0D + return;=0D +}=0D +=0D +=0D +/**=0D + This function inited the flash platform.=0D +=0D + @param None.=0D +=0D + @retval EFI_SUCCESS NorFlashPlatformInitialization() is execut= ed successfully.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformInitialization (=0D + VOID=0D + )=0D +{=0D +=0D + mCmdWrite =3D 0x2;=0D + mCmdErase =3D 0xD8;=0D + mCmdPp =3D 0x6;=0D +=0D + mSpiMasterProtocol->SpiInit();=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +/**=0D + This function geted the flash device information.=0D +=0D + @param[out] NorFlashDevices the pointer to store flash device informa= tion.=0D + @param[out] Count the number of the flash device.=0D +=0D + @retval EFI_SUCCESS NorFlashPlatformGetDevices() is executed s= uccessfully.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformGetDevices (=0D + OUT NOR_FLASH_DEVICE_DESCRIPTION *NorFlashDevices=0D + )=0D +{=0D + *NorFlashDevices =3D mNorFlashDevices;=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +/**=0D + This function readed flash content form the specified area of flash.=0D +=0D + @param[in] Address The address of the flash.=0D + @param[in] Buffer The pointer of the Buffer to be stored.=0D + @param[out] Length The bytes readed form flash.=0D +=0D + @retval EFI_SUCCESS NorFlashPlatformRead() is executed succes= sfully.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformRead (=0D + IN UINTN Address,=0D + IN VOID *Buffer,=0D + OUT UINT32 Length=0D + )=0D +{=0D +=0D + CopyMem ((VOID *)Buffer, (VOID *)Address, Length);=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +/**=0D + This function erased one block flash content.=0D +=0D + @param[in] BlockAddress the BlockAddress to be erased.=0D +=0D + @retval EFI_SUCCESS NorFlashPlatformEraseSingleBlock() is exe= cuted successfully.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformEraseSingleBlock (=0D + IN UINTN BlockAddress=0D + )=0D +{=0D +=0D + NorFlashPlatformEraseSector ( BlockAddress);=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +/**=0D + This function erased the flash content of the specified area.=0D +=0D + @param[in] Offset the offset of the flash.=0D + @param[in] Length length to be erased.=0D +=0D + @retval EFI_SUCCESS NorFlashPlatformErase() is executed succe= ssfully.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformErase (=0D + IN UINT64 Offset,=0D + IN UINT64 Length=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINT64 Index;=0D + UINT64 Count;=0D +=0D + Status =3D EFI_SUCCESS;=0D + if ((Length % SIZE_64KB) =3D=3D 0) {=0D + Count =3D Length / SIZE_64KB;=0D + for (Index =3D 0; Index < Count; Index++) {=0D + NorFlashPlatformEraseSingleBlock (Offset);=0D + Offset +=3D SIZE_64KB;=0D + }=0D + } else {=0D + Status =3D EFI_INVALID_PARAMETER;=0D + }=0D +=0D + return Status;=0D +}=0D +=0D +=0D +/**=0D + This function writed data to flash.=0D +=0D + @param[in] Address the address of the flash.=0D +=0D + @param[in] Buffer the pointer of the Buffer to be writed.=0D +=0D + @param[in] BufferSizeInBytes the bytes of the Buffer.=0D +=0D + @retval EFI_SUCCESS NorFlashPlatformWrite() is executed succe= ssfully.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformWrite (=0D + IN UINTN Address,=0D + IN VOID *Buffer,=0D + IN UINT32 BufferSizeInBytes=0D + )=0D +{=0D + UINT32 Index;=0D + UINT32 Remainder;=0D + UINT32 Quotient;=0D + EFI_STATUS Status;=0D + UINTN TmpAddress;=0D +=0D + TmpAddress =3D Address;=0D + Remainder =3D BufferSizeInBytes % 256;=0D + Quotient =3D BufferSizeInBytes / 256;=0D +=0D + if (BufferSizeInBytes <=3D 256) {=0D + Status =3D NorFlashWrite256 (TmpAddress, Buffer, BufferSizeInBytes);=0D + } else {=0D + for (Index =3D 0; Index < Quotient; Index++) {=0D + Status =3D NorFlashWrite256 (TmpAddress, Buffer, 256);=0D + TmpAddress +=3D 256;=0D + Buffer +=3D 256;=0D + }=0D +=0D + if (Remainder !=3D 0) {=0D + Status =3D NorFlashWrite256 (TmpAddress, Buffer, Remainder);=0D + }=0D + }=0D +=0D + if (EFI_ERROR (Status)) {=0D + ASSERT_EFI_ERROR (Status);=0D + }=0D +=0D + return EFI_SUCCESS;=0D +=0D +}=0D +=0D +=0D +/**=0D + This function inited the flash driver protocol.=0D +=0D + @param[in] NorFlashProtocol A pointer to the norflash protocol struct= .=0D +=0D + @retval EFI_SUCCESS NorFlashPlatformInitProtocol() is executed suc= cessfully.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformInitProtocol (=0D + IN EFI_NORFLASH_DRV_PROTOCOL *NorFlashProtocol=0D + )=0D +{=0D + NorFlashProtocol->Initialization =3D NorFlashPlatformInitialization;= =0D + NorFlashProtocol->GetDevices =3D NorFlashPlatformGetDevices;=0D + NorFlashProtocol->Erase =3D NorFlashPlatformErase;=0D + NorFlashProtocol->EraseSingleBlock =3D NorFlashPlatformEraseSingleBlock= ;=0D + NorFlashProtocol->Read =3D NorFlashPlatformRead;=0D + NorFlashProtocol->Write =3D NorFlashPlatformWrite;=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +/**=0D + This function is the entrypoint of the norflash driver.=0D +=0D + @param[in] ImageHandle The firmware allocated handle for the EFI imag= e.=0D +=0D + @param[in] SystemTable A pointer to the EFI System Table.=0D +=0D + @retval EFI_SUCCESS The entry point is executed successfully.=0D +=0D + @retval other Some error occurs when executing this entry po= int.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformEntryPoint (=0D + IN EFI_HANDLE ImageHandle,=0D + IN EFI_SYSTEM_TABLE *SystemTable=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + Status =3D gBS->LocateProtocol (=0D + &gSpiMasterProtocolGuid,=0D + NULL,=0D + (VOID **)&mSpiMasterProtocol=0D + );=0D + if (EFI_ERROR (Status)) {=0D + return EFI_DEVICE_ERROR;=0D + }=0D +=0D + mFlashInstance =3D AllocateRuntimeZeroPool (sizeof (NorFlash_Device));=0D + if (mFlashInstance =3D=3D NULL) {=0D + return EFI_OUT_OF_RESOURCES;=0D + }=0D +=0D + NorFlashPlatformInitProtocol (&mFlashInstance->FlashProtocol);=0D +=0D + mFlashInstance->Signature =3D NORFLASH_SIGNATURE;=0D +=0D + Status =3D gBS->InstallMultipleProtocolInterfaces (=0D + &(mFlashInstance->Handle),=0D + &gSpiNorFlashProtocolGuid,=0D + &(mFlashInstance->FlashProtocol),=0D + NULL=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + //Register for the virtual address change event=0D + Status =3D gBS->CreateEventEx (=0D + EVT_NOTIFY_SIGNAL,=0D + TPL_NOTIFY,=0D + PlatformNorFlashVirtualNotifyEvent,=0D + NULL,=0D + &gEfiEventVirtualAddressChangeGuid,=0D + &mSpiNorFlashVirtualAddrChangeEvent=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + return Status;=0D +}=0D --=20 2.25.1