From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.36947.1650269652115192178 for ; Mon, 18 Apr 2022 01:14:12 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: pranav.madhu@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DA494ED1; Mon, 18 Apr 2022 01:14:10 -0700 (PDT) Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 76E083F7B4; Mon, 18 Apr 2022 01:14:09 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Sami Mujawar Subject: [edk2-platforms][PATCH V1 1/1] Platform/Sgi: Remove SLC entry from PPTT table Date: Mon, 18 Apr 2022 13:44:03 +0530 Message-Id: <20220418081403.2324-1-pranav.madhu@arm.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Remove system level cache (SLC) entry from ACPI PPTT table. SLC on the Neoverse reference design platforms is the memory side cache and so it is removed from PPTT table. Signed-off-by: Pranav Madhu --- Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 4 +--- Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 24 +++------------= ----- Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 20 +++------------= - Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc | 23 +++------------= ---- Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 21 ++++-----------= -- Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc | 21 ++++-----------= -- Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 21 ++++-----------= -- Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc | 23 ++++-----------= ---- 8 files changed, 26 insertions(+), 131 deletions(-) Link to github branch for this patch - https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/remove_slc_fro= m_pptt diff --git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h b/Platform/ARM/S= giPkg/Include/SgiAcpiHeader.h index d75d54055436..e9b6923cb035 100644 --- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h +++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h @@ -68,10 +68,8 @@ typedef struct { // PPTT processor package structure typedef struct { EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; - UINT32 ResourceOffset; - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc; RD_PPTT_MINIMAL_CLUSTER Cluster[CLUSTER_COUNT]; -} RD_PPTT_SLC_PACKAGE; +} RD_PPTT_PACKAGE; #pragma pack () =20 // diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc b/Platform= /ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc index 3615a11d75b0..0ef9607c0732 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc @@ -8,7 +8,7 @@ * Each cluster includes a 2MB L3 cache. The platform also includes a sys= tem * level cache of 8MB. * -* Copyright (c) 2021, ARM Limited. All rights reserved. +* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -168,28 +168,12 @@ #define PPTT_PACKAGE_INIT(PackageId) = \ { = \ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ - OFFSET_OF (RDE1EDGE_PPTT_PACKAGE, Slc), = \ + OFFSET_OF (RDE1EDGE_PPTT_PACKAGE, Cluster[0]), = \ PPTT_PROCESSOR_PACKAGE_FLAGS, = \ 0, = \ 0, = \ - 1 = \ + 0 = \ ), = \ - = \ - /* Offsets of the private resources */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ - Package.Slc), = \ - = \ - /* SLC parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ - PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ - 0, /* Next level of cache */ = \ - SIZE_8MB, /* Size */ = \ - 8192, /* Num of sets */ = \ - 16, /* Associativity */ = \ - PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ - ), = \ - = \ { = \ PPTT_CLUSTER_INIT (PackageId, 0), = \ PPTT_CLUSTER_INIT (PackageId, 1), = \ @@ -219,8 +203,6 @@ typedef struct { =20 typedef struct { EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; - UINT32 Offset; - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc; RDE1EDGE_PPTT_CLUSTER Cluster[CLUSTER_COUNT]; } RDE1EDGE_PPTT_PACKAGE; =20 diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc b/Platform= /ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc index 63056939a868..923ee9014970 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc @@ -8,7 +8,7 @@ * cache. Each cluster includes a 2MB L3 cache. The platform also include= s a * system level cache of 8MB. * -* Copyright (c) 2021, ARM Limited. All rights reserved. +* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -132,8 +132,6 @@ #pragma pack(1) typedef struct { EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; - UINT32 Offset; - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc; RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT]; } RDN1EDGE_PPTT_PACKAGE ; =20 @@ -157,21 +155,9 @@ STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TA= BLE Pptt =3D { =20 { EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( - OFFSET_OF (RDN1EDGE_PPTT_PACKAGE , Slc), - PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1), + OFFSET_OF (RDN1EDGE_PPTT_PACKAGE , Cluster[0]), + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0), =20 - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, - Package.Slc), - - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( - PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ - 0, /* Next level of cache */ - SIZE_8MB, /* Size */ - 8192, /* Num of sets */ - 16, /* Associativity */ - PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ - 64 /* Line size */ - ), { PPTT_CLUSTER_INIT (0, 0), PPTT_CLUSTER_INIT (0, 1), diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc b/Platfo= rm/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc index fa80544b61aa..d78afb00c3b0 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc @@ -10,7 +10,7 @@ * cluster includes a 2MB L3 cache. Each instance of the chip includes a = system * level cache of 8MB. * -* Copyright (c) 2021, ARM Limited. All rights reserved. +* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -140,26 +140,11 @@ #define PPTT_PACKAGE_INIT(PackageId) = \ { = \ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ - OFFSET_OF (RDN1EDGEX2_PPTT_PACKAGE , Slc), /* Length */ = \ + OFFSET_OF (RDN1EDGEX2_PPTT_PACKAGE , Cluster[0]), /* Length */ = \ PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */ = \ 0, /* Parent */ = \ 0, /* ACPI Id */ = \ - 1 /* Num of private resource */ = \ - ), = \ - = \ - /* Offsets of the private resources */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ - Package[PackageId].Slc), = \ - = \ - /* SLC parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ - PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ - 0, /* Next level of cache */ = \ - SIZE_8MB, /* Size */ = \ - 8192, /* Num of sets */ = \ - 16, /* Associativity */ = \ - PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 0 /* Num of private resource */ = \ ), = \ = \ { = \ @@ -171,8 +156,6 @@ #pragma pack(1) typedef struct { EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; - UINT32 Offset; - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc; RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT]; } RDN1EDGEX2_PPTT_PACKAGE; =20 diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc b/Platform/ARM= /SgiPkg/AcpiTables/RdN2/Pptt.aslc index b70d583ba90c..2ee566145382 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc @@ -7,7 +7,7 @@ * cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also i= ncludes * system level cache of 32MB. * -* Copyright (c) 2021, ARM Limited. All rights reserved. +* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -116,7 +116,7 @@ */ typedef struct { EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; - RD_PPTT_SLC_PACKAGE Package; + RD_PPTT_PACKAGE Package; } EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; #pragma pack () =20 @@ -131,21 +131,8 @@ STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TA= BLE Pptt =3D { =20 { EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( - OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc), - PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1), - - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, - Package.Slc), - - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( - PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ - 0, /* Next level of cache */ - SIZE_32MB, /* Size */ - 32768, /* Num of sets */ - 16, /* Associativity */ - PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ - 64 /* Line size */ - ), + OFFSET_OF (RD_PPTT_PACKAGE, Cluster[0]), + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0), =20 { PPTT_CLUSTER_INIT (0, 0), diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc b/Platform= /ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc index 5890544c0b92..54eb6d6c41b3 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc @@ -7,7 +7,7 @@ * L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache. The platfor= m also * includes system level cache of 8MB. * -* Copyright (c) 2021, ARM Limited. All rights reserved. +* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. * SPDX-License-Identifier: BSD-2-Clause-Patent * * @par Specification Reference: @@ -115,7 +115,7 @@ */ typedef struct { EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; - RD_PPTT_SLC_PACKAGE Package; + RD_PPTT_PACKAGE Package; } EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; #pragma pack () =20 @@ -130,21 +130,8 @@ STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TA= BLE Pptt =3D { =20 { EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( - OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc), - PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1), - - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, - Package.Slc), - - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( - PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ - 0, /* Next level of cache */ - SIZE_8MB, /* Size */ - 8192, /* Num of sets */ - 16, /* Associativity */ - PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ - 64 /* Line size */ - ), + OFFSET_OF (RD_PPTT_PACKAGE, Cluster[0]), + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0), =20 { PPTT_CLUSTER_INIT (0, 0), diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc b/Platform/ARM= /SgiPkg/AcpiTables/RdV1/Pptt.aslc index 06f059810fb2..d8b73c804898 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc @@ -7,7 +7,7 @@ * CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2 = cache. * The platform also includes a system level cache of 16MB. * -* Copyright (c) 2021, ARM Limited. All rights reserved. +* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -116,7 +116,7 @@ */ typedef struct { EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; - RD_PPTT_SLC_PACKAGE Package; + RD_PPTT_PACKAGE Package; } EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; #pragma pack () =20 @@ -131,21 +131,8 @@ STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TA= BLE Pptt =3D { =20 { EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( - OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc), - PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1), - - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, - Package.Slc), - - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( - PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ - 0, /* Next level of cache */ - SIZE_16MB, /* Size */ - 16384, /* Num of sets */ - 16, /* Associativity */ - PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ - 64 /* Line size */ - ), + OFFSET_OF (RD_PPTT_PACKAGE, Cluster[0]), + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0), =20 { PPTT_CLUSTER_INIT (0, 0), diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc b/Platform/A= RM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc index 607a9eac9dc0..82124ca2ab65 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc @@ -9,7 +9,7 @@ * cache and 1MB L2 cache. The platform also includes a system level cach= e of * 16MB per chip. * -* Copyright (c) 2021, ARM Limited. All rights reserved. +* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -121,27 +121,12 @@ #define PPTT_PACKAGE_INIT(PackageId) = \ { = \ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ - OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc), /* Length */ = \ + OFFSET_OF (RD_PPTT_PACKAGE, Cluster[0]), /* Length */ = \ PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */ = \ 0, /* Parent */ = \ 0, /* ACPI Id */ = \ - 1 /* Num of private resource *= / \ + 0 /* Num of private resource *= / \ ), = \ - = \ - /* Offsets of the private resources */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ - Package[PackageId].Slc), = \ - = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ - PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ - 0, /* Next level of cache */ = \ - SIZE_16MB, /* Size */ = \ - 16384, /* Num of sets */ = \ - 16, /* Associativity */ = \ - PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ - ), = \ - = \ { = \ PPTT_CLUSTER_INIT (PackageId, 0), = \ PPTT_CLUSTER_INIT (PackageId, 1), = \ @@ -156,7 +141,7 @@ */ typedef struct { EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; - RD_PPTT_SLC_PACKAGE Package[CHIP_= COUNT]; + RD_PPTT_PACKAGE Package[CHIP_= COUNT]; } EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; #pragma pack () =20 --=20 2.17.1