From: "Pranav Madhu" <pranav.madhu@arm.com>
To: devel@edk2.groups.io
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>,
Sami Mujawar <sami.mujawar@arm.com>
Subject: [edk2-platforms][PATCH V2 5/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-E1-Edge platform
Date: Mon, 18 Apr 2022 17:24:27 +0530 [thread overview]
Message-ID: <20220418115431.30602-6-pranav.madhu@arm.com> (raw)
In-Reply-To: <20220418115431.30602-1-pranav.madhu@arm.com>
Update the Rd-E1-Edge platform specific ACPI tables to ACPI version
v6.4.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc | 247 ++++++++++----------
Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 106 ++++-----
2 files changed, 181 insertions(+), 172 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
index cb70394bfe91..0b2bba575bf5 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-E1-Edge
+ platform is included in this table.
+
+ Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
-#include <IndustryStandard/Acpi.h>
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -21,173 +27,174 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts;
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTURE GicIts;
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
- // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
+ // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
- // Efficiency)
+ // Efficiency,
+ // SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
// (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-0 Thread-0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-0 Thread-0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-1
- 0, 1, GET_MPID(0x0, 0x1), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-1
+ 0, 1, GET_MPID(0x0, 0x1), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-0
- 0, 2, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-0
+ 0, 2, GET_MPID(0x0, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-1
- 0, 3, GET_MPID(0x0, 0x101), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-1
+ 0, 3, GET_MPID(0x0, 0x101), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-2 Thread-0
- 0, 4, GET_MPID(0x0, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-2 Thread-0
+ 0, 4, GET_MPID(0x0, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-2 Thread-1
- 0, 5, GET_MPID(0x0, 0x201), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-2 Thread-1
+ 0, 5, GET_MPID(0x0, 0x201), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-3 Thread-0
- 0, 6, GET_MPID(0x0, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-3 Thread-0
+ 0, 6, GET_MPID(0x0, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-3 Thread-1
- 0, 7, GET_MPID(0x0, 0x301), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-3 Thread-1
+ 0, 7, GET_MPID(0x0, 0x301), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-4 Thread-0
- 0, 8, GET_MPID(0x0, 0x400), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-4 Thread-0
+ 0, 8, GET_MPID(0x0, 0x400), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-4 Thread-1
- 0, 9, GET_MPID(0x0, 0x401), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-4 Thread-1
+ 0, 9, GET_MPID(0x0, 0x401), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-5 Thread-0
- 0, 10, GET_MPID(0x0, 0x500), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-5 Thread-0
+ 0, 10, GET_MPID(0x0, 0x500), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-5 Thread-1
- 0, 11, GET_MPID(0x0, 0x501), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-5 Thread-1
+ 0, 11, GET_MPID(0x0, 0x501), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-6 Thread-0
- 0, 12, GET_MPID(0x0, 0x600), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-6 Thread-0
+ 0, 12, GET_MPID(0x0, 0x600), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-6 Thread-1
- 0, 13, GET_MPID(0x0, 0x601), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-6 Thread-1
+ 0, 13, GET_MPID(0x0, 0x601), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-7 Thread-0
- 0, 14, GET_MPID(0x0, 0x700), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-7 Thread-0
+ 0, 14, GET_MPID(0x0, 0x700), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-7 Thread-1
- 0, 15, GET_MPID(0x0, 0x701), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-7 Thread-1
+ 0, 15, GET_MPID(0x0, 0x701), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
//Cluster 1
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-0 Thread-0
- 0, 16, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-0 Thread-0
+ 0, 16, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-1
- 0, 17, GET_MPID(0x100, 0x1), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-1
+ 0, 17, GET_MPID(0x100, 0x1), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-0
- 0, 18, GET_MPID(0x100, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-0
+ 0, 18, GET_MPID(0x100, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-1
- 0, 19, GET_MPID(0x100, 0x101), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-1
+ 0, 19, GET_MPID(0x100, 0x101), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-2 Thread-0
- 0, 20, GET_MPID(0x100, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-2 Thread-0
+ 0, 20, GET_MPID(0x100, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-2 Thread-1
- 0, 21, GET_MPID(0x100, 0x201), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-2 Thread-1
+ 0, 21, GET_MPID(0x100, 0x201), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-3 Thread-0
- 0, 22, GET_MPID(0x100, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-3 Thread-0
+ 0, 22, GET_MPID(0x100, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-3 Thread-1
- 0, 23, GET_MPID(0x100, 0x301), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-3 Thread-1
+ 0, 23, GET_MPID(0x100, 0x301), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-4 Thread-0
- 0, 24, GET_MPID(0x100, 0x400), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-4 Thread-0
+ 0, 24, GET_MPID(0x100, 0x400), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-4 Thread-1
- 0, 25, GET_MPID(0x100, 0x401), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-4 Thread-1
+ 0, 25, GET_MPID(0x100, 0x401), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-5 Thread-0
- 0, 26, GET_MPID(0x100, 0x500), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-5 Thread-0
+ 0, 26, GET_MPID(0x100, 0x500), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-5 Thread-1
- 0, 27, GET_MPID(0x100, 0x501), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-5 Thread-1
+ 0, 27, GET_MPID(0x100, 0x501), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-6 Thread-0
- 0, 28, GET_MPID(0x100, 0x600), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-6 Thread-0
+ 0, 28, GET_MPID(0x100, 0x600), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-6 Thread-1
- 0, 29, GET_MPID(0x100, 0x601), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-6 Thread-1
+ 0, 29, GET_MPID(0x100, 0x601), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-7 Thread-0
- 0, 30, GET_MPID(0x100, 0x700), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-7 Thread-0
+ 0, 30, GET_MPID(0x100, 0x700), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-7 Thread-1
- 0, 31, GET_MPID(0x100, 0x701), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-7 Thread-1
+ 0, 31, GET_MPID(0x100, 0x701), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
},
// GIC Distributor Entry
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
0, 3),
// GIC Redistributor
- EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
+ EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
SIZE_8MB),
// GIC ITS
- EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000)
+ EFI_ACPI_6_4_GIC_ITS_INIT(0, 0x30040000)
};
//
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
index 0ef9607c0732..fea5ac6e74db 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
@@ -1,28 +1,26 @@
/** @file
-* Processor Properties Topology Table (PPTT) for RD-E1-Edge platform
-*
-* This file describes the topological structure of the processor block on the
-* RD-E1-Edge platform in the form as defined by ACPI PPTT table. The RD-E1-Edge
-* platform includes two clusters with eight dual-thread CPUS. Each of the CPUs
-* include 32KB L1 Data cache, 32KB L1 Instruction cache and 256KB L2 cache.
-* Each cluster includes a 2MB L3 cache. The platform also includes a system
-* level cache of 8MB.
-*
-* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-* @par Specification Reference:
-* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+ Processor Properties Topology Table (PPTT) for RD-E1-Edge platform
+
+ This file describes the topological structure of the processor block on the
+ RD-E1-Edge platform in the form as defined by ACPI PPTT table. The RD-E1-Edge
+ platform includes two clusters with eight dual-thread CPUS. Each of the CPUs
+ include 32KB L1 Data cache, 32KB L1 Instruction cache and 256KB L2 cache.
+ Each cluster includes a 2MB L3 cache. The platform also includes a system
+ level cache of 8MB.
+
+ Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology Table
**/
-#include <IndustryStandard/Acpi.h>
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
-
-#include "SgiPlatform.h"
#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define THREAD_PER_CORE_E1 2
@@ -35,10 +33,10 @@
**/
#define PPTT_THREAD_INIT(PackageId, ClusterId, CpuId, ThreadId) \
{ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
sizeof (RDE1EDGE_PPTT_THREAD), /* Length */ \
PPTT_PROCESSOR_THREAD_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId]), /* Parent */ \
((PackageId << 5) | (ClusterId << 4) | (CpuId << 1) | ThreadId), \
/* ACPI Id */ \
@@ -55,10 +53,10 @@
#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) \
{ \
/* Parameters for CPU Core */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
OFFSET_OF (RDE1EDGE_PPTT_CORE, DCache), /* Length */ \
PPTT_PROCESSOR_CORE_THREADED_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId]), /* Parent */ \
0, /* ACPI Id */ \
2 /* Num of private resource */ \
@@ -66,47 +64,50 @@
\
/* Offsets of the private resources */ \
{ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].DCache), \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].ICache) \
}, \
\
/* L1 data cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
/* Next level of cache */ \
SIZE_32KB, /* Size */ \
128, /* Num of sets */ \
4, /* Associativity */ \
PPTT_DATA_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ (((PackageId << 3) | (ClusterId << 2) | CpuId) + 1) /* Cache id */ \
), \
\
/* L1 instruction cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
/* Next level of cache */ \
SIZE_32KB, /* Size */ \
128, /* Num of sets */ \
4, /* Associativity */ \
PPTT_INST_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ (((PackageId << 3) | (ClusterId << 2) | CpuId) + 1) /* Cache id */ \
), \
\
/* L2 cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
0, /* Next level of cache */ \
SIZE_256KB, /* Size */ \
1024, /* Num of sets */ \
4, /* Associativity */ \
PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ (((PackageId << 3) | (ClusterId << 2) | CpuId) + 1) /* Cache id */ \
), \
\
/* Thread Initialization */ \
@@ -124,28 +125,29 @@
#define PPTT_CLUSTER_INIT(PackageId, ClusterId) \
{ \
/* Parameters for Cluster */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
OFFSET_OF (RDE1EDGE_PPTT_CLUSTER, L3Cache), /* Length */ \
PPTT_PROCESSOR_CLUSTER_THREADED_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package), /* Parent */ \
0, /* ACPI Id */ \
1 /* Num of private resource */ \
), \
\
/* Offsets of the private resources */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].L3Cache), \
\
/* L3 cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
0, /* Next level of cache */ \
SIZE_2MB, /* Size */ \
2048, /* Num of sets */ \
16, /* Associativity */ \
PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ (((PackageId << 1) | ClusterId) + 1) /* Cache id */ \
), \
\
/* Initialize child cores */ \
@@ -167,7 +169,7 @@
**/
#define PPTT_PACKAGE_INIT(PackageId) \
{ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
OFFSET_OF (RDE1EDGE_PPTT_PACKAGE, Cluster[0]), \
PPTT_PROCESSOR_PACKAGE_FLAGS, \
0, \
@@ -182,27 +184,27 @@
#pragma pack(1)
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Thread;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Thread;
} RDE1EDGE_PPTT_THREAD;
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Core;
UINT32 Offset[2];
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE DCache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE ICache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE L2Cache;
RDE1EDGE_PPTT_THREAD Thread[THREAD_PER_CORE_E1];
} RDE1EDGE_PPTT_CORE;
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Cluster;
UINT32 Offset;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE L3Cache;
RDE1EDGE_PPTT_CORE Core[CORE_COUNT / THREAD_PER_CORE_E1];
} RDE1EDGE_PPTT_CLUSTER;
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Package;
RDE1EDGE_PPTT_CLUSTER Cluster[CLUSTER_COUNT];
} RDE1EDGE_PPTT_PACKAGE;
@@ -210,17 +212,17 @@ typedef struct {
* Processor Properties Topology Table
*/
typedef struct {
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
RDE1EDGE_PPTT_PACKAGE Package;
-} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
)
},
--
2.17.1
next prev parent reply other threads:[~2022-04-18 11:54 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-18 11:54 [edk2-platforms][PATCH V2 0/9] Upadate the ACPI tables for RD platforms Pranav Madhu
2022-04-18 11:54 ` [edk2-platforms][PATCH V2 1/9] Platform/Sgi: Update ACPI version to v6.4 Pranav Madhu
2022-04-18 11:54 ` [edk2-platforms][PATCH V2 2/9] Platform/Sgi: Update ACPI version to v6.4 for SGI-575 platform Pranav Madhu
2022-04-18 11:54 ` [edk2-platforms][PATCH V2 3/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-N1-Edge platform Pranav Madhu
2022-04-18 11:54 ` [edk2-platforms][PATCH V2 4/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-N1-Edge-X2 platform Pranav Madhu
2022-04-18 11:54 ` Pranav Madhu [this message]
2022-04-18 11:54 ` [edk2-platforms][PATCH V2 6/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-V1 platform Pranav Madhu
2022-04-18 11:54 ` [edk2-platforms][PATCH V2 7/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-V1-MC platform Pranav Madhu
2022-04-18 11:54 ` [edk2-platforms][PATCH V2 8/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-N2 platform Pranav Madhu
2022-04-18 11:54 ` [edk2-platforms][PATCH V2 9/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-N2-Cfg1 platform Pranav Madhu
2022-04-18 20:09 ` [edk2-devel] [edk2-platforms][PATCH V2 0/9] Upadate the ACPI tables for RD platforms Thomas Abraham
2022-06-20 16:52 ` Pranav Madhu
2022-06-21 15:55 ` PierreGondois
2022-06-22 5:33 ` Pranav Madhu
2022-04-20 7:40 ` Ard Biesheuvel
2022-04-20 8:06 ` Pranav Madhu
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