public inbox for devel@edk2.groups.io
 help / color / mirror / Atom feed
From: "Pranav Madhu" <pranav.madhu@arm.com>
To: devel@edk2.groups.io
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>,
	Sami Mujawar <sami.mujawar@arm.com>
Subject: [edk2-platforms][PATCH V2 6/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-V1 platform
Date: Mon, 18 Apr 2022 17:24:28 +0530	[thread overview]
Message-ID: <20220418115431.30602-7-pranav.madhu@arm.com> (raw)
In-Reply-To: <20220418115431.30602-1-pranav.madhu@arm.com>

Update the Rd-V1 platform specific ACPI tables to ACPI version v6.4.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
 Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc | 159 ++++++++++----------
 Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc |  77 +++++-----
 2 files changed, 122 insertions(+), 114 deletions(-)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc
index c4551e92c0f2..374b0e2bddbf 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc
@@ -1,18 +1,24 @@
 /** @file
-*  Multiple APIC Description Table (MADT)
-*
-*  Copyright (c) 2020, Arm Limited. All rights reserved.
-*
-*  SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+  Multiple APIC Description Table (MADT)
+
+  The MADT table provides OSPM with information necessary  for operation on
+  systems with Generic interrupt controller (GIC). The information about the GIC
+  CPU interface, redistributor, distributor and ITS blocks on the Rd-V1 platform
+  is included in this table.
+
+  Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+    - ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
 **/
 
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
 #include <Library/AcpiLib.h>
 #include <Library/ArmLib.h>
 #include <Library/PcdLib.h>
-#include <IndustryStandard/Acpi.h>
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
 
 #define CORE_CNT   (FixedPcdGet32 (PcdClusterCount) * \
                       FixedPcdGet32 (PcdCoreCount))
@@ -21,110 +27,111 @@
 #pragma pack (1)
 
 typedef struct {
-  EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;
-  EFI_ACPI_6_2_GIC_STRUCTURE                            GicInterfaces[CORE_CNT];
-  EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE                GicDistributor;
-  EFI_ACPI_6_2_GICR_STRUCTURE                           GicRedistributor;
-  EFI_ACPI_6_2_GIC_ITS_STRUCTURE                        GicIts[4];
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+  EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;
+  EFI_ACPI_6_4_GIC_STRUCTURE                            GicInterfaces[CORE_CNT];
+  EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE                GicDistributor;
+  EFI_ACPI_6_4_GICR_STRUCTURE                           GicRedistributor;
+  EFI_ACPI_6_4_GIC_ITS_STRUCTURE                        GicIts[4];
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
 
 #pragma pack ()
 
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
   {
     ARM_ACPI_HEADER (
-      EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
-      EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
-      EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+      EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+      EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+      EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
     ),
     // MADT specific fields
     0, // LocalApicAddress
     0  // Flags
   },
   {
-    // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
+    // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
     //                                          PmuIrq, GicBase, GicVBase,
     //                                          GicHBase, GsivId, GicRBase,
-    //                                          Efficiency)
+    //                                          Efficiency,
+    //                                          SpeOverflowInterrupt)
     // Note: The GIC Structure of the primary CPU must be the first entry
-    // (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
-    EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0
-      0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+    // (see note in 5.2.12.14 GICC Structure of ACPI v6.4).
+    EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core0
+      0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
       FixedPcdGet32 (PcdGicDistributorBase),
-      0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-    EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1
-      0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+      0x2c020000, 0x2c010000, 25, 0, 0, 0),
+    EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core1
+      0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
       FixedPcdGet32 (PcdGicDistributorBase),
-      0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-    EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2
-      0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+      0x2c020000, 0x2c010000, 25, 0, 0, 0),
+    EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core2
+      0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
       FixedPcdGet32 (PcdGicDistributorBase),
-      0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-    EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core3
-      0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+      0x2c020000, 0x2c010000, 25, 0, 0, 0),
+    EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core3
+      0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
       FixedPcdGet32 (PcdGicDistributorBase),
-      0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-    EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core4
-      0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+      0x2c020000, 0x2c010000, 25, 0, 0, 0),
+    EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core4
+      0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
       FixedPcdGet32 (PcdGicDistributorBase),
-      0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-    EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core5
-      0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+      0x2c020000, 0x2c010000, 25, 0, 0, 0),
+    EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core5
+      0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
       FixedPcdGet32 (PcdGicDistributorBase),
-      0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-    EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core6
-      0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+      0x2c020000, 0x2c010000, 25, 0, 0, 0),
+    EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core6
+      0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
       FixedPcdGet32 (PcdGicDistributorBase),
-      0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-    EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core7
-      0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+      0x2c020000, 0x2c010000, 25, 0, 0, 0),
+    EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core7
+      0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
       FixedPcdGet32 (PcdGicDistributorBase),
-      0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-    EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core8
-      0, 8, GET_MPID(0x800, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+      0x2c020000, 0x2c010000, 25, 0, 0, 0),
+    EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core8
+      0, 8, GET_MPID(0x800, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
       FixedPcdGet32 (PcdGicDistributorBase),
-      0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-    EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core9
-      0, 9, GET_MPID(0x900, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+      0x2c020000, 0x2c010000, 25, 0, 0, 0),
+    EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core9
+      0, 9, GET_MPID(0x900, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
       FixedPcdGet32 (PcdGicDistributorBase),
-      0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-    EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core10
-      0, 10, GET_MPID(0xa00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+      0x2c020000, 0x2c010000, 25, 0, 0, 0),
+    EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core10
+      0, 10, GET_MPID(0xa00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
       FixedPcdGet32 (PcdGicDistributorBase),
-      0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-    EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core11
-      0, 11, GET_MPID(0xb00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+      0x2c020000, 0x2c010000, 25, 0, 0, 0),
+    EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core11
+      0, 11, GET_MPID(0xb00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
       FixedPcdGet32 (PcdGicDistributorBase),
-      0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-    EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core12
-      0, 12, GET_MPID(0xc00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+      0x2c020000, 0x2c010000, 25, 0, 0, 0),
+    EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core12
+      0, 12, GET_MPID(0xc00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
       FixedPcdGet32 (PcdGicDistributorBase),
-      0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-    EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core13
-      0, 13, GET_MPID(0xd00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+      0x2c020000, 0x2c010000, 25, 0, 0, 0),
+    EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core13
+      0, 13, GET_MPID(0xd00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
       FixedPcdGet32 (PcdGicDistributorBase),
-      0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-    EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core14
-      0, 14, GET_MPID(0xe00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+      0x2c020000, 0x2c010000, 25, 0, 0, 0),
+    EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core14
+      0, 14, GET_MPID(0xe00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
       FixedPcdGet32 (PcdGicDistributorBase),
-      0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-    EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core15
-      0, 15, GET_MPID(0xf00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+      0x2c020000, 0x2c010000, 25, 0, 0, 0),
+    EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core15
+      0, 15, GET_MPID(0xf00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
       FixedPcdGet32 (PcdGicDistributorBase),
-      0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+      0x2c020000, 0x2c010000, 25, 0, 0, 0),
   },
   // GIC Distributor Entry
-  EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
+  EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
                                     0, 3),
   // GIC Redistributor
-  EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
+  EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
                                       SIZE_16MB),
   // GIC ITS
   {
-    EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000),
-    EFI_ACPI_6_2_GIC_ITS_INIT(1, 0x30080000),
-    EFI_ACPI_6_2_GIC_ITS_INIT(2, 0x300C0000),
-    EFI_ACPI_6_2_GIC_ITS_INIT(3, 0x30100000),
+    EFI_ACPI_6_4_GIC_ITS_INIT(0, 0x30040000),
+    EFI_ACPI_6_4_GIC_ITS_INIT(1, 0x30080000),
+    EFI_ACPI_6_4_GIC_ITS_INIT(2, 0x300C0000),
+    EFI_ACPI_6_4_GIC_ITS_INIT(3, 0x30100000),
   },
 };
 
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc
index d8b73c804898..19ea429c7baa 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc
@@ -1,27 +1,25 @@
 /** @file
-* Processor Properties Topology Table (PPTT) for RD-V1 single-chip platform
-*
-* This file describes the topological structure of the processor block on the
-* RD-V1 single-chip platform in the form as defined by ACPI PPTT table. The
-* RD-V1 single-chip platform includes sixteen single-thread CPUS. Each of the
-* CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache.
-* The platform also includes a system level cache of 16MB.
-*
-* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-* @par Specification Reference:
-*   - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+  Processor Properties Topology Table (PPTT) for RD-V1 single-chip platform
+
+  This file describes the topological structure of the processor block on the
+  RD-V1 single-chip platform in the form as defined by ACPI PPTT table. The
+  RD-V1 single-chip platform includes sixteen single-thread CPUS. Each of the
+  CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache.
+  The platform also includes a system level cache of 16MB.
+
+  Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+    - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology Table
 **/
 
-#include <IndustryStandard/Acpi.h>
 #include <Library/AcpiLib.h>
 #include <Library/ArmLib.h>
 #include <Library/PcdLib.h>
-
-#include "SgiPlatform.h"
 #include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
 
 /** Define helper macro for populating processor core information.
 
@@ -32,10 +30,10 @@
 #define PPTT_CORE_INIT(PackageId, ClusterId, CpuId)                            \
   {                                                                            \
     /* Parameters for CPU Core */                                              \
-    EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (                               \
+    EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT (                               \
       OFFSET_OF (RD_PPTT_CORE, DCache),     /* Length */                       \
       PPTT_PROCESSOR_CORE_FLAGS,            /* Flag */                         \
-      OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,             \
+      OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,             \
         Package.Cluster[ClusterId]),        /* Parent */                       \
       ((PackageId << 4) | ClusterId),       /* ACPI Id */                      \
       2                                     /* Num of private resource */      \
@@ -43,47 +41,50 @@
                                                                                \
     /* Offsets of the private resources */                                     \
     {                                                                          \
-      OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,             \
+      OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,             \
           Package.Cluster[ClusterId].Core[CpuId].DCache),                      \
-      OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,             \
+      OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,             \
           Package.Cluster[ClusterId].Core[CpuId].ICache)                       \
     },                                                                         \
                                                                                \
     /* L1 data cache parameters */                                             \
-    EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (                                   \
+    EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT (                                   \
       PPTT_CACHE_STRUCTURE_FLAGS,           /* Flag */                         \
-      OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,             \
+      OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,             \
         Package.Cluster[ClusterId].Core[CpuId].L2Cache),                       \
                                             /* Next level of cache */          \
       SIZE_64KB,                            /* Size */                         \
       256,                                  /* Num of sets */                  \
       4,                                    /* Associativity */                \
       PPTT_DATA_CACHE_ATTR,                 /* Attributes */                   \
-      64                                    /* Line size */                    \
+      64,                                   /* Line size */                    \
+      (((PackageId << 4) | ClusterId) + 1)  /* Cache id */                     \
     ),                                                                         \
                                                                                \
     /* L1 instruction cache parameters */                                      \
-    EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (                                   \
+    EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT (                                   \
       PPTT_CACHE_STRUCTURE_FLAGS,           /* Flag */                         \
-      OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,             \
+      OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,             \
         Package.Cluster[ClusterId].Core[CpuId].L2Cache),                       \
                                             /* Next level of cache */          \
       SIZE_64KB,                            /* Size */                         \
       256,                                  /* Num of sets */                  \
       4,                                    /* Associativity */                \
       PPTT_INST_CACHE_ATTR,                 /* Attributes */                   \
-      64                                    /* Line size */                    \
+      64,                                   /* Line size */                    \
+      (((PackageId << 4) | ClusterId) + 1)  /* Cache id */                     \
     ),                                                                         \
                                                                                \
     /* L2 cache parameters */                                                  \
-    EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (                                   \
+    EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT (                                   \
       PPTT_CACHE_STRUCTURE_FLAGS,           /* Flag */                         \
       0,                                    /* Next level of cache */          \
       SIZE_1MB,                             /* Size */                         \
       2048,                                 /* Num of sets */                  \
       8,                                    /* Associativity */                \
       PPTT_UNIFIED_CACHE_ATTR,              /* Attributes */                   \
-      64                                    /* Line size */                    \
+      64,                                   /* Line size */                    \
+      (((PackageId << 4) | ClusterId) + 1)  /* Cache id */                     \
     ),                                                                         \
   }
 
@@ -95,10 +96,10 @@
 #define PPTT_CLUSTER_INIT(PackageId, ClusterId)                                \
   {                                                                            \
     /* Parameters for Cluster */                                               \
-    EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (                               \
+    EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT (                               \
       OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core),  /* Length */                 \
       PPTT_PROCESSOR_CLUSTER_FLAGS,         /* Flag */                         \
-      OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,             \
+      OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,             \
         Package),                           /* Parent */                       \
       ((PackageId << 4) | ClusterId),       /* ACPI Id */                      \
       0                                     /* Num of private resource */      \
@@ -115,22 +116,22 @@
  * Processor Properties Topology Table
  */
 typedef struct {
-  EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER  Header;
+  EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER  Header;
   RD_PPTT_PACKAGE                                          Package;
-} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
 #pragma pack ()
 
-STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
   {
     ARM_ACPI_HEADER (
-      EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
-      EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
-      EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+      EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+      EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+      EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
     )
   },
 
   {
-    EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
+    EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT (
       OFFSET_OF (RD_PPTT_PACKAGE, Cluster[0]),
       PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0),
 
-- 
2.17.1


  parent reply	other threads:[~2022-04-18 11:54 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-18 11:54 [edk2-platforms][PATCH V2 0/9] Upadate the ACPI tables for RD platforms Pranav Madhu
2022-04-18 11:54 ` [edk2-platforms][PATCH V2 1/9] Platform/Sgi: Update ACPI version to v6.4 Pranav Madhu
2022-04-18 11:54 ` [edk2-platforms][PATCH V2 2/9] Platform/Sgi: Update ACPI version to v6.4 for SGI-575 platform Pranav Madhu
2022-04-18 11:54 ` [edk2-platforms][PATCH V2 3/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-N1-Edge platform Pranav Madhu
2022-04-18 11:54 ` [edk2-platforms][PATCH V2 4/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-N1-Edge-X2 platform Pranav Madhu
2022-04-18 11:54 ` [edk2-platforms][PATCH V2 5/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-E1-Edge platform Pranav Madhu
2022-04-18 11:54 ` Pranav Madhu [this message]
2022-04-18 11:54 ` [edk2-platforms][PATCH V2 7/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-V1-MC platform Pranav Madhu
2022-04-18 11:54 ` [edk2-platforms][PATCH V2 8/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-N2 platform Pranav Madhu
2022-04-18 11:54 ` [edk2-platforms][PATCH V2 9/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-N2-Cfg1 platform Pranav Madhu
2022-04-18 20:09 ` [edk2-devel] [edk2-platforms][PATCH V2 0/9] Upadate the ACPI tables for RD platforms Thomas Abraham
2022-06-20 16:52   ` Pranav Madhu
2022-06-21 15:55     ` PierreGondois
2022-06-22  5:33       ` Pranav Madhu
2022-04-20  7:40 ` Ard Biesheuvel
2022-04-20  8:06   ` Pranav Madhu

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-list from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220418115431.30602-7-pranav.madhu@arm.com \
    --to=devel@edk2.groups.io \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox