From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mx.groups.io with SMTP id smtpd.web09.5680.1650613054305445902 for ; Fri, 22 Apr 2022 00:37:34 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=ghoEgysC; spf=pass (domain: redhat.com, ip: 170.10.133.124, mailfrom: kraxel@redhat.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1650613053; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QCBC0hJxA1MB41iIK+ILJGqOfWmdWE2OKyg9vwBO7uc=; b=ghoEgysCAo1Xf1z9k1HbA7+jJPzdZdsWc95VDjj5ftbvM4GyiRR67mP9BY64l0AVh3rK2a pbmBTkTmySt8LHL5/bMSxXl2fq9jAlTwBXjKBORbtM3V7dzgJqMcLwPCIPtGqChfzqWS75 tMx0f1e29u4RD3IbDUtPfSL1Z6xoUe0= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-554-aBgS1xztM4mDiXAJxsJEOA-1; Fri, 22 Apr 2022 03:37:29 -0400 X-MC-Unique: aBgS1xztM4mDiXAJxsJEOA-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.rdu2.redhat.com [10.11.54.5]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id F1E2980B710; Fri, 22 Apr 2022 07:37:28 +0000 (UTC) Received: from sirius.home.kraxel.org (unknown [10.39.192.9]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 5329C9D7E; Fri, 22 Apr 2022 07:37:18 +0000 (UTC) Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id ACA6D1800795; Fri, 22 Apr 2022 09:37:13 +0200 (CEST) From: "Gerd Hoffmann" To: devel@edk2.groups.io Cc: Pawel Polawski , Ard Biesheuvel , Liming Gao , Hao A Wu , Ray Ni , Oliver Steffen , Leif Lindholm , Jordan Justen , Jiewen Yao , Gerd Hoffmann , Abner Chang , Jian J Wang Subject: [PATCH v5 3/6] OvmfPkg/Platform: unfix PcdPciExpressBaseAddress Date: Fri, 22 Apr 2022 09:37:10 +0200 Message-Id: <20220422073713.2087781-4-kraxel@redhat.com> In-Reply-To: <20220422073713.2087781-1-kraxel@redhat.com> References: <20220422073713.2087781-1-kraxel@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.11.54.5 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=kraxel@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="US-ASCII"; x-default=true Will be set by FdtPciHostBridgeLib, so it can't be an fixed when we want use that library. Signed-off-by: Gerd Hoffmann --- OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf | 4 +++- OvmfPkg/PlatformPei/PlatformPei.inf | 2 +- OvmfPkg/Library/PlatformInitLib/MemDetect.c | 4 ++-- OvmfPkg/Library/PlatformInitLib/Platform.c | 4 ++-- 4 files changed, 8 insertions(+), 6 deletions(-) diff --git a/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf b/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf index d0fab5cc1f4f..d2a0bec43452 100644 --- a/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf +++ b/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf @@ -54,8 +54,10 @@ [LibraryClasses] [LibraryClasses.X64] TdxLib -[FixedPcd] +[Pcd] gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + +[FixedPcd] gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/PlatformPei.inf index 00372fa0ebb5..3cd83e6ec3e5 100644 --- a/OvmfPkg/PlatformPei/PlatformPei.inf +++ b/OvmfPkg/PlatformPei/PlatformPei.inf @@ -95,6 +95,7 @@ [Pcd] gUefiOvmfPkgTokenSpaceGuid.PcdXenPvhStartOfDayStructPtr gUefiOvmfPkgTokenSpaceGuid.PcdXenPvhStartOfDayStructPtrSize gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved @@ -118,7 +119,6 @@ [Pcd] [FixedPcd] gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidSize - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType diff --git a/OvmfPkg/Library/PlatformInitLib/MemDetect.c b/OvmfPkg/Library/PlatformInitLib/MemDetect.c index 4c1dedf863c3..83a7b6726bb7 100644 --- a/OvmfPkg/Library/PlatformInitLib/MemDetect.c +++ b/OvmfPkg/Library/PlatformInitLib/MemDetect.c @@ -61,8 +61,8 @@ PlatformQemuUc32BaseInitialization ( // [PcdPciExpressBaseAddress, 4GB) range require a very small number of // variable MTRRs (preferably 1 or 2). // - ASSERT (FixedPcdGet64 (PcdPciExpressBaseAddress) <= MAX_UINT32); - PlatformInfoHob->Uc32Base = (UINT32)FixedPcdGet64 (PcdPciExpressBaseAddress); + ASSERT (PcdGet64 (PcdPciExpressBaseAddress) <= MAX_UINT32); + PlatformInfoHob->Uc32Base = (UINT32)PcdGet64 (PcdPciExpressBaseAddress); return; } diff --git a/OvmfPkg/Library/PlatformInitLib/Platform.c b/OvmfPkg/Library/PlatformInitLib/Platform.c index 101074f6100d..60a30a01f3b5 100644 --- a/OvmfPkg/Library/PlatformInitLib/Platform.c +++ b/OvmfPkg/Library/PlatformInitLib/Platform.c @@ -154,7 +154,7 @@ PlatformMemMapInitialization ( // The MMCONFIG area is expected to fall between the top of low RAM and // the base of the 32-bit PCI host aperture. // - PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress); + PciExBarBase = PcdGet64 (PcdPciExpressBaseAddress); ASSERT (TopOfLowRam <= PciExBarBase); ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB); PciBase = (UINT32)(PciExBarBase + SIZE_256MB); @@ -278,7 +278,7 @@ PciExBarInitialization ( // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice // for DXE's page tables to cover the MMCONFIG area. // - PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress); + PciExBarBase.Uint64 = PcdGet64 (PcdPciExpressBaseAddress); ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0); ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0); -- 2.35.1