From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mx.groups.io with SMTP id smtpd.web08.27791.1650882899998265904 for ; Mon, 25 Apr 2022 03:35:00 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=ciDEta4v; spf=pass (domain: redhat.com, ip: 170.10.133.124, mailfrom: kraxel@redhat.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1650882899; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=A5OqnEmu4+plwPASf84GHGOuxPRuRd65gD6HWedH3ec=; b=ciDEta4vL2nUC4wFt67lrrRhcrk3lIcK9dDI+rFQyqnaWbb0NdwJzyK1qeyEXPXPkFWvsY /Ac/pCYdE+HHtavGGrcbskDH9pxk9QambgGMomleuwwClhQHkqXdke6J+1bZ4hnDNO1t+F S/4s06Mb/6zLfMXZ9aGpr4I7nJp30L8= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-644-YNmcAYP3MWGqgEc5reD86w-1; Mon, 25 Apr 2022 06:34:55 -0400 X-MC-Unique: YNmcAYP3MWGqgEc5reD86w-1 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.rdu2.redhat.com [10.11.54.8]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 798D9185A7BA; Mon, 25 Apr 2022 10:34:54 +0000 (UTC) Received: from sirius.home.kraxel.org (unknown [10.39.192.9]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 4051AC27EAE; Mon, 25 Apr 2022 10:34:54 +0000 (UTC) Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id DA8F7180062F; Mon, 25 Apr 2022 12:34:46 +0200 (CEST) From: "Gerd Hoffmann" To: devel@edk2.groups.io Cc: Jiewen Yao , Oliver Steffen , Leif Lindholm , Pawel Polawski , Hao A Wu , Abner Chang , Liming Gao , Ray Ni , Jordan Justen , Jian J Wang , Ard Biesheuvel , Gerd Hoffmann Subject: [PATCH v6 5/6] OvmfPkg/Microvm/pcie: mPhysMemAddressWidth tweak Date: Mon, 25 Apr 2022 12:34:45 +0200 Message-Id: <20220425103446.496763-6-kraxel@redhat.com> In-Reply-To: <20220425103446.496763-1-kraxel@redhat.com> References: <20220425103446.496763-1-kraxel@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.85 on 10.11.54.8 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=kraxel@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="US-ASCII"; x-default=true microvm places the 64bit mmio space at the end of the physical address space. So mPhysMemAddressWidth must be correct, otherwise the pci host bridge setup throws an error because it thinks the 64bit mmio window is not addressable. On microvm we can simply use standard cpuid to figure the address width because the host-phys-bits option (-cpu ${name},host-phys-bits=on) is forced to be enabled. Side note: For 'pc' and 'q35' this is not the case for backward compatibility reasons. Signed-off-by: Gerd Hoffmann --- OvmfPkg/Library/PlatformInitLib/MemDetect.c | 41 +++++++++++++++++++++ OvmfPkg/PlatformPei/Platform.c | 2 +- 2 files changed, 42 insertions(+), 1 deletion(-) diff --git a/OvmfPkg/Library/PlatformInitLib/MemDetect.c b/OvmfPkg/Library/PlatformInitLib/MemDetect.c index 83a7b6726bb7..c28d7601f87e 100644 --- a/OvmfPkg/Library/PlatformInitLib/MemDetect.c +++ b/OvmfPkg/Library/PlatformInitLib/MemDetect.c @@ -491,6 +491,42 @@ PlatformGetFirstNonAddress ( return FirstNonAddress; } +/* + * Use CPUID to figure physical address width. Does *not* work + * reliable on qemu. For historical reasons qemu returns phys-bits=40 + * even in case the host machine supports less than that. + * + * qemu has a cpu property (host-phys-bits={on,off}) to change that + * and make sure guest phys-bits are not larger than host phys-bits., + * but it is off by default. Exception: microvm machine type + * hard-wires that property to on. + */ +VOID +EFIAPI +PlatformAddressWidthFromCpuid ( + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + UINT32 RegEax; + + AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); + if (RegEax >= 0x80000008) { + AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); + PlatformInfoHob->PhysMemAddressWidth = (UINT8)RegEax; + } else { + PlatformInfoHob->PhysMemAddressWidth = 36; + } + + PlatformInfoHob->FirstNonAddress = LShiftU64 (1, PlatformInfoHob->PhysMemAddressWidth); + + DEBUG (( + DEBUG_INFO, + "%a: cpuid: phys-bits is %d\n", + __FUNCTION__, + PlatformInfoHob->PhysMemAddressWidth + )); +} + /** Initialize the PhysMemAddressWidth field in PlatformInfoHob based on guest RAM size. **/ @@ -503,6 +539,11 @@ PlatformAddressWidthInitialization ( UINT64 FirstNonAddress; UINT8 PhysMemAddressWidth; + if (PlatformInfoHob->HostBridgeDevId == 0xffff /* microvm */) { + PlatformAddressWidthFromCpuid (PlatformInfoHob); + return; + } + // // As guest-physical memory size grows, the permanent PEI RAM requirements // are dominated by the identity-mapping page tables built by the DXE IPL. diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index f006755d5fdb..009db67ee60a 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -357,12 +357,12 @@ InitializePlatform ( S3Verification (); BootModeInitialization (&mPlatformInfoHob); - AddressWidthInitialization (&mPlatformInfoHob); // // Query Host Bridge DID // mPlatformInfoHob.HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID); + AddressWidthInitialization (&mPlatformInfoHob); MaxCpuCountInitialization (&mPlatformInfoHob); -- 2.35.1