From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f181.google.com (mail-pf1-f181.google.com [209.85.210.181]) by mx.groups.io with SMTP id smtpd.web12.7162.1652171130823087990 for ; Tue, 10 May 2022 01:25:30 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=RCwIpqd9; spf=pass (domain: linaro.org, ip: 209.85.210.181, mailfrom: masahisa.kojima@linaro.org) Received: by mail-pf1-f181.google.com with SMTP id j6so14324248pfe.13 for ; Tue, 10 May 2022 01:25:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=ymzF69FU52UtcvnL3IcYpsvTOqcz5w+foWenPFlqV8A=; b=RCwIpqd9ESUb7er0woWgegBubD/OQG4uJPjSkdtTUeLkTe2yu0DGAPKzXfzNPrOkCv SA4SWTHsz48Yc+QoPff17H0w8s2KY9yIDyChW8fX2BBozuMoyscKJ2RO9EX7Ni2qNIQN R01dZkB1S4Q3qfF681yIEHxwh8KpdNZiYKt+FrwuRDkmOErGntyaffi3nba1MWHNh1hy 24irtSy8n3HbKvlaHCoAmHWQ5xqn8xCCjJeFyC8iedgxIAZIUQq2YV4FRRUnM0WUKFtO n9sewODm45vmRVnfFy60S/QZXtKnb22UzSa6TDnDmWPxR0fSlH61iGzQWK7aaGiTMDRH 2d7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=ymzF69FU52UtcvnL3IcYpsvTOqcz5w+foWenPFlqV8A=; b=0uneJkPDt+10RPYaqPqqMLRqP29qTDlvCLcVijtZXK9FO5b1cwe01ywGwZnHIKCWx+ 7c7ofFMV7j97RbZv7mSXWAytvi+Lcopy5UlSOexIW2cmIeZjO3fEFfOGmxwISmGsH5EF HXWr8rOUGhbgYRB6Qv6VgPZmkeHzx5f4Yp5PkiR6WV+8rYRVlY/3IpARpMA0vUO8H3RD qVx4gtpTx4NPA9RiiwXsitiiuTyki0maCQvTlmZZN6YQf4Xnrv0jKp7NxaFiYhII9K48 yFfqLCV/rLhpu5jfB4PW/ewnQ1G6oPeX+vwDfCoZrRtukilTsDcNbRJ0Ekh0JxFBWZJ0 KBhg== X-Gm-Message-State: AOAM531JSw5k2Hf6Ww03ZVN+uQcT9dEdDv5NL44ntEJzUJJejhGMLlAR 8p985JIijUSbWGqgZtEKHOCQqnxZXsXiWQ== X-Google-Smtp-Source: ABdhPJzJmcQiKEQJtRHhjjiaZ7aQSW13gI74ypusxwPONd0L6Cs4ZRoW1UM4PCqs1kuJAxOuHheztQ== X-Received: by 2002:a05:6a00:729:b0:4f7:77ed:c256 with SMTP id 9-20020a056a00072900b004f777edc256mr19594965pfm.1.1652171130128; Tue, 10 May 2022 01:25:30 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([240d:1a:cf7:5800:82fa:5bff:fe4b:26b1]) by smtp.gmail.com with ESMTPSA id ep22-20020a17090ae65600b001dbce368a9dsm1213687pjb.5.2022.05.10.01.25.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 May 2022 01:25:29 -0700 (PDT) From: "Masahisa Kojima" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Kazuhiko Sakamoto , Masahisa Kojima Subject: [PATCH edk2-platforms 1/1] Silicon/SynQuacer/Fip006Dxe: Support 4-bytes address for erase and write Date: Tue, 10 May 2022 17:25:18 +0900 Message-Id: <20220510082518.12346-1-masahisa.kojima@linaro.org> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Kazuhiko Sakamoto Support 4-bytes address for erase and write, so that we can access whole region of SPI-NOR Flash(64MiB) implemented on the Developerbox. This commit also fixes the wrong macro name. SPINOR_OP_SE and SPINOR_OP_SE_4B is the commoand for 64KB block erase, it must be SPINOR_OP_BE and SPINOR_OP_BE_4B. Signed-off-by: Masahisa Kojima --- Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.h | 4 ++-- Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.c | 13 +++++-------- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.h b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.h index bade5706e6ae..3cb86ab588e0 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.h +++ b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.h @@ -313,7 +313,7 @@ NorFlashReadID ( #define SPINOR_OP_BE_4K_PMC 0xd7 // Erase 4KiB block on PMC chips #define SPINOR_OP_BE_32K 0x52 // Erase 32KiB block #define SPINOR_OP_CHIP_ERASE 0xc7 // Erase whole flash chip -#define SPINOR_OP_SE 0xd8 // Sector erase (usually 64KiB) +#define SPINOR_OP_BE 0xd8 // Block erase (usually 64KiB) #define SPINOR_OP_RDID 0x9f // Read JEDEC ID #define SPINOR_OP_RDSFDP 0x5a // Read SFDP #define SPINOR_OP_RDCR 0x35 // Read configuration register @@ -329,7 +329,7 @@ NorFlashReadID ( #define SPINOR_OP_PP_1_4_4_4B 0x3e // Quad page program #define SPINOR_OP_BE_4K_4B 0x21 // Erase 4KiB block #define SPINOR_OP_BE_32K_4B 0x5c // Erase 32KiB block -#define SPINOR_OP_SE_4B 0xdc // Sector erase (usually 64KiB) +#define SPINOR_OP_BE_4B 0xdc // Block erase (usually 64KiB) #define SPINOR_OP_RD_ARRAY 0xe8 // Read array #define SPINOR_OP_RD_NVCFG 0xb5 // Read non-volatile config register #define SPINOR_OP_RD_VCR 0x85 // Read VCR register diff --git a/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.c b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.c index 8cdaa0eeb83f..b2ca0033ac13 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.c +++ b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.c @@ -51,12 +51,10 @@ STATIC CONST CSDC_DEFINITION mN25qCSDCDefTable[] = { { SPINOR_OP_READ_4B, TRUE, TRUE, FALSE, FALSE, CS_CFG_MBM_SINGLE, CSDC_TRP_SINGLE }, // Write Operations - { SPINOR_OP_PP, TRUE, FALSE, FALSE, TRUE, CS_CFG_MBM_SINGLE, - CSDC_TRP_SINGLE }, - { SPINOR_OP_PP_1_1_4, TRUE, FALSE, FALSE, TRUE, CS_CFG_MBM_QUAD, + { SPINOR_OP_PP_4B, TRUE, TRUE, FALSE, TRUE, CS_CFG_MBM_SINGLE, CSDC_TRP_SINGLE }, // Erase Operations - { SPINOR_OP_SE, FALSE, FALSE, FALSE, TRUE, CS_CFG_MBM_SINGLE, + { SPINOR_OP_BE_4B, FALSE, FALSE, FALSE, TRUE, CS_CFG_MBM_SINGLE, CSDC_TRP_SINGLE }, }; @@ -446,9 +444,8 @@ NorFlashEraseSingleBlock ( BlockAddress -= Instance->RegionBaseAddress; BlockAddress += Instance->OffsetLba * Instance->BlockSize; - NorFlashSetHostCSDC (Instance, TRUE, mFip006NullCmdSeq); - MmioWrite32 (Instance->DeviceBaseAddress, - SwapBytes32 (BlockAddress & 0x00FFFFFF) | SPINOR_OP_SE); + NorFlashSetHostCommand (Instance, SPINOR_OP_BE_4B); + MmioWrite32 (Instance->DeviceBaseAddress, SwapBytes32 (BlockAddress)); NorFlashWaitProgramErase (Instance); NorFlashSetHostCSDC (Instance, TRUE, mFip006NullCmdSeq); @@ -515,7 +512,7 @@ NorFlashWriteSingleWord ( if (EFI_ERROR (NorFlashEnableWrite (Instance))) { return EFI_DEVICE_ERROR; } - NorFlashSetHostCommand (Instance, SPINOR_OP_PP); + NorFlashSetHostCommand (Instance, SPINOR_OP_PP_4B); MmioWrite32 (WordAddress, WriteData); NorFlashWaitProgramErase (Instance); -- 2.17.1