From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.2953.1652757526879566433 for ; Mon, 16 May 2022 20:18:47 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=Nt7ARXz6; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: chasel.chiu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652757526; x=1684293526; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=6TCWeZiOej9+Cxa4GtHDvioZrZ57883AHcPFz7rVMUs=; b=Nt7ARXz6vwCatZ9cfQs8NqYEVlxmhSsSObdlSZ+jQqwGsICsJCrEwsRf pp8ZOyCbNrksUeG0i09/lPN93WRBf8VdXuCdnY7OhjkWm3xY7T9mDqMTm 0rnfYQPLJTMKzpj/4elyj8j5fva+bhsogq5fGhTdli/qoDw3zGKPBNf0F +T5uPjex3LZgh54Clrp9suVQ3bDfDr2OCQ/iRyswjyF+ZF3qTFigC0mQa QqSfE9M6CJu7fSkN/xtuluNhETVtmu9+Ap9QlzHdUK9HjTX9zqgv0Qj7H 1PMuEg+5Eq5Zh+wq56KFfov0pxy9fzs6suieT74jpuB47kghllLFnBgx+ Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10349"; a="251552422" X-IronPort-AV: E=Sophos;i="5.91,231,1647327600"; d="scan'208";a="251552422" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 May 2022 20:18:45 -0700 X-IronPort-AV: E=Sophos;i="5.91,231,1647327600"; d="scan'208";a="596876377" Received: from cchiu4-mobl.gar.corp.intel.com ([10.252.185.137]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 May 2022 20:18:44 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Ankit Sinha , Chasel Chiu , Nate DeSimone , Liming Gao , Eric Dong Subject: [PATCH V1 1/1] MinPlatformPkg: Add PCDs to update FADT entries from board package Date: Tue, 17 May 2022 11:18:30 +0800 Message-Id: <20220517031830.1520-1-chasel.chiu@intel.com> X-Mailer: git-send-email 2.28.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Ankit Sinha Adds new PCDs to allow entries in FADT to be customized during platform integration. Board packages will can update these PCDs during boot. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Eric Dong Signed-off-by: Ankit Sinha --- Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 85 ++++++= ++++++-------- Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf | 24 ++++++ Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec | 36 ++++++= +-- 3 files changed, 105 insertions(+), 40 deletions(-) diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c b= /Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c index 05fc7799fb13..b3d067def3fa 100644 --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c @@ -1165,6 +1165,11 @@ PlatformUpdateTables ( // Update the creator revision=0D //=0D TableHeader->CreatorRevision =3D PcdGet32(PcdAcpiDefaultCreatorRevis= ion);=0D +=0D + //=0D + // Update the oem revision=0D + //=0D + TableHeader->OemRevision =3D PcdGet32(PcdAcpiDefaultOemRevision);=0D }=0D }=0D =0D @@ -1187,44 +1192,54 @@ PlatformUpdateTables ( case EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE:=0D FadtHeader =3D (EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *) Table;=0D =0D - FadtHeader->PreferredPmProfile =3D PcdGet8 (PcdFadtPreferredPmProfile)= ;=0D - FadtHeader->IaPcBootArch =3D PcdGet16 (PcdFadtIaPcBootArch);=0D - FadtHeader->Flags =3D PcdGet32 (PcdFadtFlags);=0D + FadtHeader->PreferredPmProfile =3D PcdGet8 (PcdFadtPref= erredPmProfile);=0D + FadtHeader->IaPcBootArch =3D PcdGet16 (PcdFadtIaP= cBootArch);=0D + FadtHeader->Flags =3D PcdGet32 (PcdFadtFla= gs);=0D + FadtHeader->AcpiEnable =3D PcdGet8 (PcdAcpiEnab= leSwSmi);=0D + FadtHeader->AcpiDisable =3D PcdGet8 (PcdAcpiDisa= bleSwSmi);=0D + FadtHeader->Pm1aEvtBlk =3D PcdGet16 (PcdAcpiPm1= AEventBlockAddress);=0D + FadtHeader->Pm1bEvtBlk =3D PcdGet16 (PcdAcpiPm1= BEventBlockAddress);=0D + FadtHeader->Pm1aCntBlk =3D PcdGet16 (PcdAcpiPm1= AControlBlockAddress);=0D + FadtHeader->Pm1bCntBlk =3D PcdGet16 (PcdAcpiPm1= BControlBlockAddress);=0D + FadtHeader->Pm2CntBlk =3D PcdGet16 (PcdAcpiPm2= ControlBlockAddress);=0D + FadtHeader->PmTmrBlk =3D PcdGet16 (PcdAcpiPmT= imerBlockAddress);=0D + FadtHeader->Gpe0Blk =3D PcdGet16 (PcdAcpiGpe= 0BlockAddress);=0D + FadtHeader->Gpe0BlkLen =3D PcdGet8 (PcdAcpiGpe0= BlockLength);=0D + FadtHeader->Gpe1Blk =3D PcdGet16 (PcdAcpiGpe= 1BlockAddress);=0D + FadtHeader->Gpe1Base =3D PcdGet8 (PcdAcpiGpe1= Base);=0D + FadtHeader->DutyWidth =3D PcdGet8 (PcdAcpiDuty= Width);=0D =0D - FadtHeader->AcpiEnable =3D PcdGet8 (PcdAcpiEnableSwSmi);=0D - FadtHeader->AcpiDisable =3D PcdGet8 (PcdAcpiDisableSwSmi);=0D + FadtHeader->XPm1aEvtBlk.Address =3D PcdGet16 (PcdAcpiPm1= AEventBlockAddress);=0D + FadtHeader->XPm1aCntBlk.Address =3D PcdGet16 (PcdAcpiPm1= AControlBlockAddress);=0D + FadtHeader->XPm1bCntBlk.Address =3D PcdGet16 (PcdAcpiPm1= BControlBlockAddress);=0D + FadtHeader->XPm2CntBlk.Address =3D PcdGet16 (PcdAcpiPm2= ControlBlockAddress);=0D + FadtHeader->XPmTmrBlk.Address =3D PcdGet16 (PcdAcpiPmT= imerBlockAddress);=0D + FadtHeader->XGpe0Blk.Address =3D PcdGet16 (PcdAcpiGpe= 0BlockAddress);=0D + FadtHeader->XGpe1Blk.Address =3D PcdGet16 (PcdAcpiGpe= 1BlockAddress);=0D =0D - FadtHeader->Pm1aEvtBlk =3D PcdGet16 (PcdAcpiPm1AEventBlockAddress);=0D - FadtHeader->Pm1bEvtBlk =3D PcdGet16 (PcdAcpiPm1BEventBlockAddress);=0D - FadtHeader->Pm1aCntBlk =3D PcdGet16 (PcdAcpiPm1AControlBlockAddress);= =0D - FadtHeader->Pm1bCntBlk =3D PcdGet16 (PcdAcpiPm1BControlBlockAddress);= =0D - FadtHeader->Pm2CntBlk =3D PcdGet16 (PcdAcpiPm2ControlBlockAddress);=0D - FadtHeader->PmTmrBlk =3D PcdGet16 (PcdAcpiPmTimerBlockAddress);=0D - FadtHeader->Gpe0Blk =3D PcdGet16 (PcdAcpiGpe0BlockAddress);=0D - FadtHeader->Gpe0BlkLen =3D 0x20;=0D - FadtHeader->Gpe1Blk =3D PcdGet16 (PcdAcpiGpe1BlockAddress);=0D + FadtHeader->ResetReg.AccessSize =3D PcdGet8 (PcdAcpiRese= tRegAccessSize);=0D + FadtHeader->XPm1aEvtBlk.AccessSize =3D PcdGet8 (PcdAcpiXPm1= aEvtBlkAccessSize);=0D + FadtHeader->XPm1bEvtBlk.AccessSize =3D PcdGet8 (PcdAcpiXPm1= bEvtBlkAccessSize);=0D + FadtHeader->XPm1aCntBlk.AccessSize =3D PcdGet8 (PcdAcpiXPm1= aCntBlkAccessSize);=0D + FadtHeader->XPm1bCntBlk.AccessSize =3D PcdGet8 (PcdAcpiXPm1= bCntBlkAccessSize);=0D + FadtHeader->XPm2CntBlk.AccessSize =3D PcdGet8 (PcdAcpiXPm2= CntBlkAccessSize);=0D + FadtHeader->XPmTmrBlk.AccessSize =3D PcdGet8 (PcdAcpiXPmT= mrBlkAccessSize);=0D + FadtHeader->XGpe0Blk.AccessSize =3D PcdGet8 (PcdAcpiXGpe= 0BlkAccessSize);=0D + FadtHeader->XGpe1Blk.AccessSize =3D PcdGet8 (PcdAcpiXGpe= 1BlkAccessSize);=0D =0D - FadtHeader->XPm1aEvtBlk.Address =3D PcdGet16 (PcdAcpiPm1AEventBlockAdd= ress);=0D - FadtHeader->XPm1bEvtBlk.Address =3D PcdGet16 (PcdAcpiPm1BEventBlockAdd= ress);=0D - if (FadtHeader->XPm1bEvtBlk.Address =3D=3D 0) {=0D - FadtHeader->XPm1bEvtBlk.AccessSize =3D 0;=0D - }=0D - FadtHeader->XPm1aCntBlk.Address =3D PcdGet16 (PcdAcpiPm1AControlBlockA= ddress);=0D - FadtHeader->XPm1bCntBlk.Address =3D PcdGet16 (PcdAcpiPm1BControlBlockA= ddress);=0D - if (FadtHeader->XPm1bCntBlk.Address =3D=3D 0) {=0D - FadtHeader->XPm1bCntBlk.AccessSize =3D 0;=0D - }=0D - FadtHeader->XPm2CntBlk.Address =3D PcdGet16 (PcdAcpiPm2ControlBlockAd= dress);=0D - //if (FadtHeader->XPm2CntBlk.Address =3D=3D 0) {=0D - FadtHeader->XPm2CntBlk.AccessSize =3D 0;=0D - //}=0D - FadtHeader->XPmTmrBlk.Address =3D PcdGet16 (PcdAcpiPmTimerBlockAddre= ss);=0D - FadtHeader->XGpe0Blk.Address =3D PcdGet16 (PcdAcpiGpe0BlockAddress)= ;=0D - FadtHeader->XGpe1Blk.Address =3D PcdGet16 (PcdAcpiGpe1BlockAddress)= ;=0D - if (FadtHeader->XGpe1Blk.Address =3D=3D 0) {=0D - FadtHeader->XGpe1Blk.AddressSpaceId =3D 0;=0D - FadtHeader->XGpe1Blk.AccessSize =3D 0;=0D - }=0D + FadtHeader->SleepControlReg.AddressSpaceId =3D PcdGet8 (PcdAcpiSlee= pControlRegAddressSpaceId);=0D + FadtHeader->SleepControlReg.RegisterBitOffset =3D PcdGet8 (PcdAcpiSlee= pControlRegRegisterBitOffset);=0D + FadtHeader->SleepControlReg.AccessSize =3D PcdGet8 (PcdAcpiSlee= pControlRegAccessSize);=0D + FadtHeader->SleepControlReg.Address =3D PcdGet64 (PcdAcpiSle= epControlRegAddress);=0D + FadtHeader->SleepStatusReg.AddressSpaceId =3D PcdGet8 (PcdAcpiSlee= pStatusRegAddressSpaceId);=0D + FadtHeader->SleepStatusReg.RegisterBitWidth =3D PcdGet8 (PcdAcpiSlee= pStatusRegRegisterBitWidth);=0D + FadtHeader->SleepStatusReg.RegisterBitOffset =3D PcdGet8 (PcdAcpiSlee= pStatusRegRegisterBitOffset);=0D + FadtHeader->SleepStatusReg.AccessSize =3D PcdGet8 (PcdAcpiSlee= pStatusRegAccessSize);=0D + FadtHeader->SleepStatusReg.Address =3D PcdGet64 (PcdAcpiSle= epStatusRegAddress);=0D +=0D + FadtHeader->S4BiosReq =3D PcdGet8 (PcdAcpiS4Bi= osReq);=0D + FadtHeader->XPm1aEvtBlk.Address =3D PcdGet16 (PcdAcpiPm1= AEventBlockAddress);=0D + FadtHeader->XPm1bEvtBlk.Address =3D PcdGet16 (PcdAcpiPm1= BEventBlockAddress);=0D =0D DEBUG ((DEBUG_INFO, "ACPI FADT table @ address 0x%x\n", Table));=0D DEBUG ((DEBUG_INFO, " IaPcBootArch 0x%x\n", FadtHeader->IaPcBootArch)= );=0D diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf= b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf index 99adf9c381c9..9d91e418d4ca 100644 --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf @@ -62,6 +62,8 @@ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount=0D =0D gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1Base=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiDutyWidth=0D gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch=0D gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags=0D =0D @@ -77,7 +79,29 @@ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress=0D gMinPlatformPkgTokenSpaceGuid.PcdAcpiPmTimerBlockAddress=0D gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockAddress=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockLength=0D gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiResetRegAccessSize=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPm1aEvtBlkAccessSize=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPm1bEvtBlkAccessSize=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPm1aCntBlkAccessSize=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPm1bCntBlkAccessSize=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPm2CntBlkAccessSize=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPmTmrBlkAccessSize=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXGpe0BlkAccessSize=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXGpe1BlkAccessSize=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiSleepControlRegAddressSpaceId=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiSleepControlRegRegisterBitWidth=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiSleepControlRegRegisterBitOffset=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiSleepControlRegAccessSize=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiSleepControlRegAddress=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiSleepStatusRegAddressSpaceId=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiSleepStatusRegRegisterBitWidth=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiSleepStatusRegRegisterBitOffset=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiSleepStatusRegAccessSize=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiSleepStatusRegAddress=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiS4BiosReq=0D +=0D =0D gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress=0D gMinPlatformPkgTokenSpaceGuid.PcdIoApicAddress=0D diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec b/Platform/In= tel/MinPlatformPkg/MinPlatformPkg.dec index e38617ce20fd..bfc50565144f 100644 --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec @@ -112,10 +112,6 @@ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8|UINT32|0x90000022=0D gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|4|UINT32|0x90000023=0D =0D - gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x02|UINT8|0x900= 00025=0D - gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0001|UINT16|0x900000= 26=0D - gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000086A5|UINT32|0x90000027= =0D -=0D gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0x65|U= INT32|0x20000500=0D gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0x30|UINT3= 2|0x20000501=0D gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402|UIN= T32|0x20000502=0D @@ -245,6 +241,10 @@ gMinPlatformPkgTokenSpaceGuid.PcdPciSegmentCount |0x1 |UI= NT8|0x4001004E=0D gMinPlatformPkgTokenSpaceGuid.PcdRandomizePlatformHierarchy |TRUE |BOOL= EAN|0x4001004F=0D =0D + gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x02|UINT8|0x900= 00025=0D + gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0001|UINT16|0x900000= 26=0D + gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000086A5|UINT32|0x90000027= =0D +=0D gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x1800|UINT16= |0x00010035=0D gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0x0000|UINT16= |0x00010036=0D gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x1804|UINT= 16|0x0001037=0D @@ -252,7 +252,33 @@ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x1850|UINT1= 6|0x00010039=0D gMinPlatformPkgTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x1808|UINT16|0= x0001003A=0D gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x1880|UINT16|0x00= 01003B=0D - gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0x0000|UINT16|0x00= 01003C=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockLength|0x00|UINT8|0x000100= 3C=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0x0000|UINT16|0x00= 01003D=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1Base|0x00|UINT8|0x00010040=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiDutyWidth|0x00|UINT8|0x00010041=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiResetRegAccessSize|0x00|UINT8|0x000= 10042=0D +=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPm1aEvtBlkAccessSize|0x00|UINT8|0x= 00010043=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPm1bEvtBlkAccessSize|0x00|UINT8|0x= 00010044=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPm1aCntBlkAccessSize|0x00|UINT8|0x= 00010045=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPm1bCntBlkAccessSize|0x00|UINT8|0x= 00010046=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPm2CntBlkAccessSize|0x00|UINT8|0x0= 0010047=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPmTmrBlkAccessSize|0x00|UINT8|0x00= 010048=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXGpe0BlkAccessSize|0x00|UINT8|0x000= 10049=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXGpe1BlkAccessSize|0x00|UINT8|0x000= 1004A=0D +=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiSleepControlRegAddressSpaceId|0x00|= UINT8|0x0001004B=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiSleepControlRegRegisterBitWidth|0x0= 0|UINT8|0x0001004C=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiSleepControlRegRegisterBitOffset|0x= 00|UINT8|0x0001004D=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiSleepControlRegAccessSize|0x00|UINT= 8|0x0001004E=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiSleepControlRegAddress|0x0000000000= 000000|UINT64|0x0001004F=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiSleepStatusRegAddressSpaceId|0x00|U= INT8|0x00010050=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiSleepStatusRegRegisterBitWidth|0x00= |UINT8|0x00010051=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiSleepStatusRegRegisterBitOffset|0x0= 0|UINT8|0x00010052=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiSleepStatusRegAccessSize|0x00|UINT8= |0x00010053=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiSleepStatusRegAddress|0x00000000000= 00000|UINT64|0x00010054=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiS4BiosReq|0x0000|UINT8|0x00010055=0D +=0D =0D gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000|UINT3= 2|0x0010004=0D gMinPlatformPkgTokenSpaceGuid.PcdFspCpuPeiApWakeupBufferAddr|0x9f000|UIN= T32|0x30000008=0D --=20 2.33.0.windows.1