From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web12.4835.1652777061061604497 for ; Tue, 17 May 2022 01:44:23 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=LzCvsGTn; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: chinni.b.duggapu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652777063; x=1684313063; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TDuFcoOIM2TW9rONlph72c8Aku9GI4CKmnvNWMd6FG4=; b=LzCvsGTnysBVECA8PEWXavNOOZN+P3apw/l9YQFVQzloPn0/wKVLccNo //+7bzZtsoABlYm6sCk34AAPRCIlW66DSVwQtLYu+TLZEqMAhHsNCGILy xdNpMgeO7oW09HFG8xb5ihRU3piuG5l9pbNnmLXVBtXJtni1J3blDeZkM m8d3v2aCwVkgVWSSemBsUbYgttKHplB7O+C9cX/QEtzmbbaPmMHoaJW0m 2Wg/FJdbIdWSTjo6d3D7nxVgSdxw3wBSddqpsCdFkTwurfq5W5lxLN5uG fTUXhblZ3hkJHsehppXdTX8jB8k0nHNsKSTIypKWfH5rakP9P4Xu53UPd g==; X-IronPort-AV: E=McAfee;i="6400,9594,10349"; a="268695137" X-IronPort-AV: E=Sophos;i="5.91,232,1647327600"; d="scan'208";a="268695137" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 May 2022 01:44:23 -0700 X-IronPort-AV: E=Sophos;i="5.91,232,1647327600"; d="scan'208";a="544805180" Received: from cbduggap-mobl1.gar.corp.intel.com ([10.215.201.76]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 May 2022 01:44:21 -0700 From: "cbduggap" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng , Ashraf Ali S Subject: [PATCH v5 1/2] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention Date: Tue, 17 May 2022 14:14:00 +0530 Message-Id: <20220517084401.1805-2-chinni.b.duggapu@intel.com> X-Mailer: git-send-email 2.36.0.windows.1 In-Reply-To: <20220517084401.1805-1-chinni.b.duggapu@intel.com> References: <20220517084401.1805-1-chinni.b.duggapu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3926 This API accept one parameter using RCX and this is consumed in mutiple sub functions. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Signed-off-by: cbduggap --- IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 39 ++++++++++--------- .../Include/SaveRestoreSseAvxNasm.inc | 28 +++++++++++++ 2 files changed, 48 insertions(+), 19 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/F= spSecCore/X64/FspApiEntryT.nasm index a9f5f28ed7..7dd89c531a 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm @@ -114,7 +114,7 @@ endstruc global ASM_PFX(LoadMicrocodeDefault)=0D ASM_PFX(LoadMicrocodeDefault):=0D ; Inputs:=0D - ; rsp -> LoadMicrocodeParams pointer=0D + ; rcx -> LoadMicrocodeParams pointer=0D ; Register Usage:=0D ; rsp Preserved=0D ; All others destroyed=0D @@ -130,10 +130,9 @@ ASM_PFX(LoadMicrocodeDefault): =0D cmp rsp, 0=0D jz ParamError=0D - mov eax, dword [rsp + 8] ; Parameter pointer=0D - cmp eax, 0=0D + cmp rcx, 0=0D jz ParamError=0D - mov esp, eax=0D + mov rsp, rcx=0D =0D ; skip loading Microcode if the MicrocodeCodeSize is zero=0D ; and report error if size is less than 2k=0D @@ -144,14 +143,14 @@ ASM_PFX(LoadMicrocodeDefault): jne ParamError=0D =0D ; UPD structure is compliant with FSP spec 2.4=0D - mov eax, dword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]=0D - cmp eax, 0=0D + mov rax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]=0D + cmp rax, 0=0D jz Exit2=0D - cmp eax, 0800h=0D + cmp rax, 0800h=0D jl ParamError=0D =0D - mov esi, dword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]=0D - cmp esi, 0=0D + mov rsi, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]=0D + cmp rsi, 0=0D jnz CheckMainHeader=0D =0D ParamError:=0D @@ -256,7 +255,8 @@ CheckAddress: ; UPD structure is compliant with FSP spec 2.4=0D ; Is automatic size detection ?=0D mov rax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]=0D - cmp rax, 0ffffffffffffffffh=0D + mov rcx, 0ffffffffffffffffh=0D + cmp rax, rcx=0D jz LoadMicrocodeDefault4=0D =0D ; Address >=3D microcode region address + microcode region size?=0D @@ -321,8 +321,7 @@ ASM_PFX(EstablishStackFsp): ;=0D ; Save parameter pointer in rdx=0D ;=0D - mov rdx, qword [rsp + 8]=0D -=0D + mov rdx, rcx=0D ;=0D ; Enable FSP STACK=0D ;=0D @@ -420,7 +419,10 @@ ASM_PFX(TempRamInitApi): ;=0D ENABLE_SSE=0D ENABLE_AVX=0D -=0D + ;=0D + ; Save Input Parameter in YMM10=0D + ;=0D + SAVE_RCX=0D ;=0D ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and YMM6=0D ;=0D @@ -442,9 +444,8 @@ ASM_PFX(TempRamInitApi): ;=0D ; Check Parameter=0D ;=0D - mov rax, qword [rsp + 8]=0D - cmp rax, 0=0D - mov rax, 08000000000000002h=0D + cmp rcx, 0=0D + mov rcx, 08000000000000002h=0D jz TempRamInitExit=0D =0D ;=0D @@ -455,18 +456,18 @@ ASM_PFX(TempRamInitApi): jnz TempRamInitExit=0D =0D ; Load microcode=0D - LOAD_RSP=0D + LOAD_RCX=0D CALL_YMM ASM_PFX(LoadMicrocodeDefault)=0D SAVE_UCODE_STATUS rax ; Save microcode return status in SLOT= 0 in YMM9 (upper 128bits).=0D ; @note If return value rax is not 0, microcode did not load, but contin= ue and attempt to boot.=0D =0D ; Call Sec CAR Init=0D - LOAD_RSP=0D + LOAD_RCX=0D CALL_YMM ASM_PFX(SecCarInit)=0D cmp rax, 0=0D jnz TempRamInitExit=0D =0D - LOAD_RSP=0D + LOAD_RCX=0D CALL_YMM ASM_PFX(EstablishStackFsp)=0D cmp rax, 0=0D jnz TempRamInitExit=0D diff --git a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc b/IntelFsp2Pkg/= Include/SaveRestoreSseAvxNasm.inc index e8bd91669d..38c807a311 100644 --- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc +++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc @@ -177,6 +177,30 @@ LXMMN xmm5, %1, 1=0D %endmacro=0D =0D +;=0D +; Upper half of YMM10 to save/restore RCX=0D +;=0D +;=0D +; Save RCX to YMM10[128:191]=0D +; Modified: XMM5 and YMM10=0D +;=0D +=0D +%macro SAVE_RCX 0=0D + LYMMN ymm10, xmm5, 1=0D + SXMMN xmm5, 0, rcx=0D + SYMMN ymm10, 1, xmm5=0D + %endmacro=0D +=0D +;=0D +; Restore RCX from YMM10[128:191]=0D +; Modified: XMM5 and RCX=0D +;=0D +=0D +%macro LOAD_RCX 0=0D + LYMMN ymm10, xmm5, 1=0D + movq rcx, xmm5=0D + %endmacro=0D +=0D ;=0D ; YMM7[128:191] for calling stack=0D ; arg 1:Entry=0D @@ -231,6 +255,7 @@ NextAddress: ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] =3D 1) to t= est=0D ; whether the processor supports SSE instruction.=0D ;=0D + mov r10, rcx=0D mov rax, 1=0D cpuid=0D bt rdx, 25=0D @@ -241,6 +266,7 @@ NextAddress: ;=0D bt ecx, 19=0D jnc SseError=0D + mov rcx, r10=0D =0D ;=0D ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)=0D @@ -258,6 +284,7 @@ NextAddress: %endmacro=0D =0D %macro ENABLE_AVX 0=0D + mov r10, rcx=0D mov eax, 1=0D cpuid=0D and ecx, 10000000h=0D @@ -280,5 +307,6 @@ EnableAvx: xgetbv ; result in edx:eax=0D or eax, 00000006h ; Set XCR0 bit #1 and bit #2 to enable = SSE state and AVX state=0D xsetbv=0D + mov rcx, r10=0D %endmacro=0D =0D --=20 2.36.0.windows.1