From: "Gerd Hoffmann" <kraxel@redhat.com>
To: devel@edk2.groups.io, zhiguang.liu@intel.com
Cc: Guo Dong <guo.dong@intel.com>, Ray Ni <ray.ni@intel.com>,
Maurice Ma <maurice.ma@intel.com>,
Benjamin You <benjamin.you@intel.com>,
Sean Rhodes <sean@starlabs.systems>
Subject: Re: [edk2-devel] [PATCH] UefiPayloadPkg: Always split page table entry to 4K if it covers stack.
Date: Tue, 31 May 2022 09:45:13 +0200 [thread overview]
Message-ID: <20220531074513.fciegyxkrgiwwqem@sirius.home.kraxel.org> (raw)
In-Reply-To: <20220531053937.19696-1-zhiguang.liu@intel.com>
On Tue, May 31, 2022 at 01:39:37PM +0800, Zhiguang Liu wrote:
> There is a concern case that stack and a proteced DXE memory range is in
> the same 2M Page Table entry, and somehow CPU doesn't flash the page
> table entry cache for stack, and causes Page fault when using stack.
Can you clarify the "somehow" please? Are we discussing a workaround
for a cpu bug here? If not this sounds like a tlbflush instruction is
missing somewhere ...
take care,
Gerd
next prev parent reply other threads:[~2022-05-31 7:45 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-31 5:39 [PATCH] UefiPayloadPkg: Always split page table entry to 4K if it covers stack Zhiguang Liu
2022-05-31 7:45 ` Gerd Hoffmann [this message]
2022-05-31 8:03 ` [edk2-devel] " Ni, Ray
2022-05-31 11:21 ` Gerd Hoffmann
2022-05-31 13:24 ` Ni, Ray
2022-05-31 15:32 ` Gerd Hoffmann
2022-06-08 0:49 ` Ni, Ray
2022-06-08 6:52 ` Gerd Hoffmann
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