From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web08.5198.1654555839570502626 for ; Mon, 06 Jun 2022 15:50:40 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=iTAbDBZy; spf=pass (domain: intel.com, ip: 134.134.136.100, mailfrom: nathaniel.l.desimone@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1654555839; x=1686091839; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=u9OuUUOzG/dqjJbDBCr+SZ+/aYEjTjxST1I0F+WSXec=; b=iTAbDBZyrrEPTt2xG0nDt1baYuL4AHJgMI8PMYkhYS2eL1rat6d/xnVf wUYQnC0EAgJBcpEnlIA7V19e+q1uke1SDumhFIhbv1L0A2rLoZYonS0yd ZiKqigOrFdPkBZ3Byd11bJbc2Bdj4MH7FN5Pv6k/myaZ5zUzQmiZbjAtx 5pzVqAmN4kmno6Oqzf1vFccAcQ7tMyabDIMOpNnz+z1NRgm96hss1bw7/ YtmCW0ivK43iXZtuTNErxKSJPvyndsDT47evmqISOcIUeE6scaX2qMvVq 6Pr0sVMEswXmxgTq3yprtVtiG9vkYgtLwPZ2dRoSDo1nzFCbkLwjJJ3s5 A==; X-IronPort-AV: E=McAfee;i="6400,9594,10370"; a="340202049" X-IronPort-AV: E=Sophos;i="5.91,280,1647327600"; d="scan'208";a="340202049" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2022 15:50:38 -0700 X-IronPort-AV: E=Sophos;i="5.91,280,1647327600"; d="scan'208";a="565186088" Received: from nldesimo-desk1.amr.corp.intel.com ([10.7.159.54]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2022 15:50:38 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Chasel Chiu , Ankit Sinha , Sai Chaganty , Michael Kubacki , Heng Luo , Deepika Kethi Reddy , Kathappan Esakkithevar , Benjamin Doron , Jeremy Soller Subject: [edk2-platforms] [PATCH V1 0/4] Enable CPU pwr mgmt in FADT for Intel client boards Date: Mon, 6 Jun 2022 15:50:26 -0700 Message-Id: <20220606225030.3403-1-nathaniel.l.desimone@intel.com> X-Mailer: git-send-email 2.27.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This patch series sets the DUTY_OFFSET and DUTY_WIDTH fields in the ACPI FADT to 1 and 3 respectively. This will enable OS power management to set the CPU clock speed in the P_CNT register on these platforms. Cc: Chasel Chiu Cc: Ankit Sinha Cc: Sai Chaganty Cc: Michael Kubacki Cc: Heng Luo Cc: Deepika Kethi Reddy Cc: Kathappan Esakkithevar Cc: Benjamin Doron Cc: Jeremy Soller Signed-off-by: Nate DeSimone Nate DeSimone (4): KabylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT WhiskeylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT CometlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT TigerlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT .../CometlakeURvp/OpenBoardPkgPcd.dsc | 9 +++- .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc | 9 +++- .../GalagoPro3/OpenBoardPkgPcd.dsc | 52 +++++++++++++++++-- .../KabylakeRvp3/OpenBoardPkgPcd.dsc | 11 +++- .../TigerlakeURvp/OpenBoardPkgPcd.dsc | 10 +++- .../UpXtreme/OpenBoardPkgPcd.dsc | 9 +++- .../WhiskeylakeURvp/OpenBoardPkgPcd.dsc | 9 +++- 7 files changed, 98 insertions(+), 11 deletions(-) -- 2.27.0.windows.1