From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web08.5199.1654555840546252063 for ; Mon, 06 Jun 2022 15:50:40 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=JF+0oMht; spf=pass (domain: intel.com, ip: 134.134.136.100, mailfrom: nathaniel.l.desimone@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1654555840; x=1686091840; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=e6AG2YAZbpPSQ86ISBrPOFzGUdceaMvQSdQrhtzrBrA=; b=JF+0oMhtTT/UBdtMyu0pgzazoWZ+TP78ZUrLqpfR6cmI6PtHtU3xsusn Wzwd09RvfpF79PgvHldAg+iJjnplPOoXp4aC4pn04rJzND77BA8Sq3Jn4 Wo2zVFt26rKYmvCcBTyUv/wVoQ5utpYEy4ndx2yX3stSqL8z20PNzUDJx ivTBp1Y18QrD5zgq2Dv1xE220tVU+pF5jFfiYH9to59RM6HMykqkKbxG8 eTb53fkunoUyg7WzvHoeaocD1PDLqvFe2yahoJq+MSv1v3unjp1gHjqy5 yJwrUk5vvy0lWRPIhaRvAbZNro9jhMAXkCdGv1AjizJ310h0Il+ajCHI5 A==; X-IronPort-AV: E=McAfee;i="6400,9594,10370"; a="340202051" X-IronPort-AV: E=Sophos;i="5.91,280,1647327600"; d="scan'208";a="340202051" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2022 15:50:38 -0700 X-IronPort-AV: E=Sophos;i="5.91,280,1647327600"; d="scan'208";a="565186094" Received: from nldesimo-desk1.amr.corp.intel.com ([10.7.159.54]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2022 15:50:38 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Chasel Chiu , Ankit Sinha , Michael Kubacki Subject: [edk2-platforms] [PATCH V1 2/4] WhiskeylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT Date: Mon, 6 Jun 2022 15:50:28 -0700 Message-Id: <20220606225030.3403-3-nathaniel.l.desimone@intel.com> X-Mailer: git-send-email 2.27.0.windows.1 In-Reply-To: <20220606225030.3403-1-nathaniel.l.desimone@intel.com> References: <20220606225030.3403-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Set the location of the DUTY_CYCLE field in the P_CNT register and indicate the width of the clock duty cycle to OS power management Cc: Chasel Chiu Cc: Ankit Sinha Cc: Michael Kubacki Signed-off-by: Nate DeSimone --- .../WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc | 9 ++++++++- .../WhiskeylakeURvp/OpenBoardPkgPcd.dsc | 9 ++++++++- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc index 84d4ec1331..8f3cc6ba28 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc @@ -1,7 +1,7 @@ ## @file # PCD configuration build description file for the UpXtreme board. # -# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2020 - 2022, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -259,6 +259,13 @@ gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber|2 gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength + # + # Set the location of the DUTY_CYCLE field in the P_CNT register + # and indicate the width of the clock duty cycle to OS power management + # + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3 + ###################################### # Platform Configuration ###################################### diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc index 4a7ba4d5f0..4a5d5ef03b 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc @@ -1,7 +1,7 @@ ## @file # PCD configuration build description file for the WhiskeylakeURvp board. # -# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -242,6 +242,13 @@ ###################################### gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength + # + # Set the location of the DUTY_CYCLE field in the P_CNT register + # and indicate the width of the clock duty cycle to OS power management + # + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3 + ###################################### # Platform Configuration ###################################### -- 2.27.0.windows.1