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From: "Nate DeSimone" <nathaniel.l.desimone@intel.com>
To: devel@edk2.groups.io
Cc: Chasel Chiu <chasel.chiu@intel.com>,
	Ankit Sinha <ankit.sinha@intel.com>,
	Michael Kubacki <michael.kubacki@microsoft.com>,
	Sai Chaganty <rangasai.v.chaganty@intel.com>,
	Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>,
	Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
Subject: [edk2-platforms] [PATCH V1 3/4] CometlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT
Date: Mon,  6 Jun 2022 15:50:29 -0700	[thread overview]
Message-ID: <20220606225030.3403-4-nathaniel.l.desimone@intel.com> (raw)
In-Reply-To: <20220606225030.3403-1-nathaniel.l.desimone@intel.com>

Set the location of the DUTY_CYCLE field in the P_CNT register
and indicate the width of the clock duty cycle to OS power management

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
Cc: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
 .../CometlakeURvp/OpenBoardPkgPcd.dsc                    | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
index 589b002d06..68dd08423b 100644
--- a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the CometlakeURvp board.
 #
-# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2020 - 2022, Intel Corporation. All rights reserved.<BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -253,6 +253,13 @@
   gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
   gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
 
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
   #
   # The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags
   #
-- 
2.27.0.windows.1


  parent reply	other threads:[~2022-06-06 22:50 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-06 22:50 [edk2-platforms] [PATCH V1 0/4] Enable CPU pwr mgmt in FADT for Intel client boards Nate DeSimone
2022-06-06 22:50 ` [edk2-platforms] [PATCH V1 1/4] KabylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT Nate DeSimone
2022-06-06 22:56   ` [edk2-devel] " Michael Kubacki
2022-06-06 23:17     ` Nate DeSimone
2022-06-06 22:50 ` [edk2-platforms] [PATCH V1 2/4] WhiskeylakeOpenBoardPkg: " Nate DeSimone
2022-06-06 22:56   ` [edk2-devel] " Michael Kubacki
2022-06-06 23:12   ` Sinha, Ankit
2022-06-06 22:50 ` Nate DeSimone [this message]
2022-06-06 22:58   ` [edk2-devel] [edk2-platforms] [PATCH V1 3/4] CometlakeOpenBoardPkg: " Michael Kubacki
2022-06-06 23:13   ` Sinha, Ankit
2022-06-06 22:50 ` [edk2-platforms] [PATCH V1 4/4] TigerlakeOpenBoardPkg: " Nate DeSimone
2022-06-06 22:59   ` [edk2-devel] " Michael Kubacki
2022-06-06 23:14   ` Sinha, Ankit
2022-06-07  1:07   ` Heng Luo
2022-06-08 22:00     ` [edk2-devel] " Michael D Kinney

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