From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web08.5199.1654555840546252063 for ; Mon, 06 Jun 2022 15:50:41 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=cSDEhfwA; spf=pass (domain: intel.com, ip: 134.134.136.100, mailfrom: nathaniel.l.desimone@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1654555840; x=1686091840; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DMSSUvJHe2Lx4NCwLDIWtojnbqB7tEgguLTY9B5vTUs=; b=cSDEhfwAHYTy3EORHToQhN/5zKFyC8Fj2gc4T7A0IpeKCm+Ghl453Nwe LfwCTK4KkE9Cfkui9r6JH2wGkfEWMhxp4e0eCLh6NVAVSwoop3lP0yLAL jXOvit2qD2BZGgsPWYAXhsFUtFGb+KdRSTsCBFcfMmQlqEReNdDd4I7JX oFwZcK5uzp8MOQPGpmYHefPfEunA6KstAfyO0kV8Zv4aNf7aGEXmyyhGl 6tMsbkTKa38NYkpdCLq+rtZs7cVzmsLyonGbqNOjo4f4oojuhTwGhu7Pz OxJR6YewBLXOCdwfIcGley4yMzEQ0p++GnQuhYs7IRdFJXOV3s2MxJ8lE w==; X-IronPort-AV: E=McAfee;i="6400,9594,10370"; a="340202052" X-IronPort-AV: E=Sophos;i="5.91,280,1647327600"; d="scan'208";a="340202052" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2022 15:50:38 -0700 X-IronPort-AV: E=Sophos;i="5.91,280,1647327600"; d="scan'208";a="565186097" Received: from nldesimo-desk1.amr.corp.intel.com ([10.7.159.54]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2022 15:50:38 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Chasel Chiu , Ankit Sinha , Michael Kubacki , Sai Chaganty , Deepika Kethi Reddy , Kathappan Esakkithevar Subject: [edk2-platforms] [PATCH V1 3/4] CometlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT Date: Mon, 6 Jun 2022 15:50:29 -0700 Message-Id: <20220606225030.3403-4-nathaniel.l.desimone@intel.com> X-Mailer: git-send-email 2.27.0.windows.1 In-Reply-To: <20220606225030.3403-1-nathaniel.l.desimone@intel.com> References: <20220606225030.3403-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Set the location of the DUTY_CYCLE field in the P_CNT register and indicate the width of the clock duty cycle to OS power management Cc: Chasel Chiu Cc: Ankit Sinha Cc: Michael Kubacki Cc: Sai Chaganty Cc: Deepika Kethi Reddy Cc: Kathappan Esakkithevar Signed-off-by: Nate DeSimone --- .../CometlakeURvp/OpenBoardPkgPcd.dsc | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc index 589b002d06..68dd08423b 100644 --- a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc @@ -1,7 +1,7 @@ ## @file # PCD configuration build description file for the CometlakeURvp board. # -# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2020 - 2022, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -253,6 +253,13 @@ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8 gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 + # + # Set the location of the DUTY_CYCLE field in the P_CNT register + # and indicate the width of the clock duty cycle to OS power management + # + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3 + # # The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags # -- 2.27.0.windows.1