From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web08.5199.1654555840546252063 for ; Mon, 06 Jun 2022 15:50:41 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=E50PJu1K; spf=pass (domain: intel.com, ip: 134.134.136.100, mailfrom: nathaniel.l.desimone@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1654555841; x=1686091841; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FJTJRQW4w1dyY3x9qit6kdAtOTG/H0T8wFsks9yIYfM=; b=E50PJu1KLVafl/JKjQbb5m4XVgH4j8sV9UCEdf/0Q0Zge1O5DKHjBDh1 AQL1eKu/isS5sqomO21B+QEpk4muVxnPGbMx8zH7n0JJZgFkkBKHVDusD xXsM0oNkfuVQtq5Q5TjT6MmBt5HiNtmHXzjHujYa5/3d37gu1BLWGQtox xQdLqgqnZRUjVzRrT19+cXw6QwHHHlGZ3LeXq8O3fEZdkKNvQgZDdalP2 3b+qfv0x6p37Eo2e0Rk5I3T/m1BxjzaGh13z1NgTMrH3edKUfDxuz+MQ0 LBchoy0Mx564xV+uE52+Nx+hCf7YZAWOvkOU/OOn5TMSwAz79x9eL5O/K w==; X-IronPort-AV: E=McAfee;i="6400,9594,10370"; a="340202053" X-IronPort-AV: E=Sophos;i="5.91,280,1647327600"; d="scan'208";a="340202053" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2022 15:50:38 -0700 X-IronPort-AV: E=Sophos;i="5.91,280,1647327600"; d="scan'208";a="565186099" Received: from nldesimo-desk1.amr.corp.intel.com ([10.7.159.54]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2022 15:50:38 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Sai Chaganty , Ankit Sinha , Michael Kubacki , Heng Luo Subject: [edk2-platforms] [PATCH V1 4/4] TigerlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT Date: Mon, 6 Jun 2022 15:50:30 -0700 Message-Id: <20220606225030.3403-5-nathaniel.l.desimone@intel.com> X-Mailer: git-send-email 2.27.0.windows.1 In-Reply-To: <20220606225030.3403-1-nathaniel.l.desimone@intel.com> References: <20220606225030.3403-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Set the location of the DUTY_CYCLE field in the P_CNT register and indicate the width of the clock duty cycle to OS power management Cc: Sai Chaganty Cc: Ankit Sinha Cc: Michael Kubacki Cc: Heng Luo Signed-off-by: Nate DeSimone --- .../TigerlakeURvp/OpenBoardPkgPcd.dsc | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc index ebbbc7b9f9..aba3c8d6d0 100644 --- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc @@ -1,7 +1,7 @@ ## @file # PCD configuration build description file for the TigerlakeURvp board. # -# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2021 - 2022, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -118,6 +118,14 @@ gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 #!endif gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x40000 + + # + # Set the location of the DUTY_CYCLE field in the P_CNT register + # and indicate the width of the clock duty cycle to OS power management + # + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3 + [PcdsFeatureFlag.common] ###################################### # Edk2 Configuration -- 2.27.0.windows.1