From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web12.5360.1654557439971488024 for ; Mon, 06 Jun 2022 16:17:20 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=MajuxlrX; spf=pass (domain: intel.com, ip: 192.55.52.120, mailfrom: nathaniel.l.desimone@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1654557439; x=1686093439; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=pYNPHBD3hHGtxbxSG0b1H8tk4Si2Kzr/Qlt+x/iWEsI=; b=MajuxlrXYYLEJyVomahNnoRiRdrefhySuQVrhOeTdhcYUaY3cAVjyapl xOa7/nvyJmsfuNnUNSfyW4GSHYoQfybcPp/8g9MvEyxb+bB2bP0riNZy6 NHqmW1yKGAiJXHmJzhMZJDDiORrGcCAMV9scMswsXr4IYtEvRfad92Abo sdZAqsj2PyeIOwGzA90fduf/Bh/kmwDfAj0UnZcoKj2Kko2yIDDV3lGWl Q+gdZ/d4Jc2GeCLWTf0BKCyb86rrqGcXhWYNkCwmFWQ047aQhS8bAN/Pu bLQRlfdRBiYXK0zXPiPe0XttpPz+iJTrQeIYdtxZknV222nGP6zfCPe62 g==; X-IronPort-AV: E=McAfee;i="6400,9594,10370"; a="275474992" X-IronPort-AV: E=Sophos;i="5.91,280,1647327600"; d="scan'208";a="275474992" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2022 16:17:19 -0700 X-IronPort-AV: E=Sophos;i="5.91,280,1647327600"; d="scan'208";a="608952569" Received: from nldesimo-desk1.amr.corp.intel.com ([10.7.159.54]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2022 16:17:19 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Chasel Chiu , Ankit Sinha , Sai Chaganty , Michael Kubacki , Heng Luo , Deepika Kethi Reddy , Kathappan Esakkithevar , Benjamin Doron , Jeremy Soller Subject: [edk2-platforms] [PATCH V2 0/4] Enable CPU pwr mgmt in FADT for Intel client boards Date: Mon, 6 Jun 2022 16:16:41 -0700 Message-Id: <20220606231645.3813-1-nathaniel.l.desimone@intel.com> X-Mailer: git-send-email 2.27.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Changes in V2: - Moved FSP dispatch mode PCD additions for GalagoPro3 to a seperate patch series This patch series sets the DUTY_OFFSET and DUTY_WIDTH fields in the ACPI FADT to 1 and 3 respectively. This will enable OS power management to set the CPU clock speed in the P_CNT register on these platforms. Cc: Chasel Chiu Cc: Ankit Sinha Cc: Sai Chaganty Cc: Michael Kubacki Cc: Heng Luo Cc: Deepika Kethi Reddy Cc: Kathappan Esakkithevar Cc: Benjamin Doron Cc: Jeremy Soller Signed-off-by: Nate DeSimone Nate DeSimone (4): KabylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT WhiskeylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT CometlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT TigerlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT .../CometlakeURvp/OpenBoardPkgPcd.dsc | 9 ++++++++- .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc | 9 ++++++++- .../GalagoPro3/OpenBoardPkgPcd.dsc | 8 +++++++- .../KabylakeRvp3/OpenBoardPkgPcd.dsc | 11 +++++++++-- .../TigerlakeURvp/OpenBoardPkgPcd.dsc | 10 +++++++++- .../UpXtreme/OpenBoardPkgPcd.dsc | 9 ++++++++- .../WhiskeylakeURvp/OpenBoardPkgPcd.dsc | 9 ++++++++- 7 files changed, 57 insertions(+), 8 deletions(-) -- 2.27.0.windows.1