From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web12.5360.1654557439971488024 for ; Mon, 06 Jun 2022 16:17:20 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=C9tDfsMU; spf=pass (domain: intel.com, ip: 192.55.52.120, mailfrom: nathaniel.l.desimone@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1654557440; x=1686093440; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=c5C9vyxFv/h4HYfitnPF2jPtOm2ajveoxluViOxlUNY=; b=C9tDfsMUk2hVfxVvN0+QA2Xx/mFgst1rmIOztlK9uFgg8iPXcygKP5oJ amzbgjCw63WD8vIy7PsUha2FDFHEbrhCeWPK9HgCa0eb0+afCD23oIuJu lSqWst5n2H+qfrT7QB8jWqxJnMaOrRm3gcFfsqeuVUZ6YeTDumwnqTV9/ Cu8TxjOyJOMsK39aWytv+zObrZ1dHBe5mCNNQKnuuSswRN0Km4dpKaMLe 3/9neQYsk1TEpL2H3bpYaFl5pKR9BoKz53/N4NW0GYZ8OdyqOY0x7Xg0V HDJqCcjy/J/hFunqqEKUQXomZyOtk/wv9AfvswxvhFGFK4hN78T3JKegJ A==; X-IronPort-AV: E=McAfee;i="6400,9594,10370"; a="275474994" X-IronPort-AV: E=Sophos;i="5.91,280,1647327600"; d="scan'208";a="275474994" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2022 16:17:19 -0700 X-IronPort-AV: E=Sophos;i="5.91,280,1647327600"; d="scan'208";a="608952575" Received: from nldesimo-desk1.amr.corp.intel.com ([10.7.159.54]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2022 16:17:19 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Chasel Chiu , Michael Kubacki Subject: [edk2-platforms] [PATCH V2 2/4] WhiskeylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT Date: Mon, 6 Jun 2022 16:16:43 -0700 Message-Id: <20220606231645.3813-3-nathaniel.l.desimone@intel.com> X-Mailer: git-send-email 2.27.0.windows.1 In-Reply-To: <20220606231645.3813-1-nathaniel.l.desimone@intel.com> References: <20220606231645.3813-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Set the location of the DUTY_CYCLE field in the P_CNT register and indicate the width of the clock duty cycle to OS power management Cc: Chasel Chiu Cc: Michael Kubacki Signed-off-by: Nate DeSimone --- .../WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc | 9 ++++++++- .../WhiskeylakeURvp/OpenBoardPkgPcd.dsc | 9 ++++++++- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc index 84d4ec1331..8f3cc6ba28 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc @@ -1,7 +1,7 @@ ## @file # PCD configuration build description file for the UpXtreme board. # -# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2020 - 2022, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -259,6 +259,13 @@ gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber|2 gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength + # + # Set the location of the DUTY_CYCLE field in the P_CNT register + # and indicate the width of the clock duty cycle to OS power management + # + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3 + ###################################### # Platform Configuration ###################################### diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc index 4a7ba4d5f0..4a5d5ef03b 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc @@ -1,7 +1,7 @@ ## @file # PCD configuration build description file for the WhiskeylakeURvp board. # -# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -242,6 +242,13 @@ ###################################### gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength + # + # Set the location of the DUTY_CYCLE field in the P_CNT register + # and indicate the width of the clock duty cycle to OS power management + # + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3 + ###################################### # Platform Configuration ###################################### -- 2.27.0.windows.1