From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web09.5398.1654557440925531581 for ; Mon, 06 Jun 2022 16:17:20 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=GQ5KjD5X; spf=pass (domain: intel.com, ip: 192.55.52.120, mailfrom: nathaniel.l.desimone@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1654557440; x=1686093440; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tGsd/Sgb3NumEHQUAMWGsK5U5jy6kxxb6HmYN2myJGE=; b=GQ5KjD5XKBXHzL6maQGXjUvICzlgrCf28I4UvdHBQB2a8feP4fWigyjQ HaXjKNRuciunmjgzJFp8jMnCB7oLpPssCs64EAHHfnUq8DJWCRWUpuXwY H7ENfS2XPKGJey+SUVLRmM+80TWr8uA21ZADv6hD4kXkmfsezdezwWjGI U4bE8hunm28lajKTAFD42nEVRBPd64ib1bZzu0Ii/CUf/u+Wa1QXMAE8e kxgGo/SEYZvwebGb+874cJMFe2up0knkRB4Iq7A8pfZ4CHzVrNiIlTvnP 9+Brn4EkQKCV8byvaGY+6pctiPEUoA+KLigtLcje8Kjbv35ivLuWPl9O0 A==; X-IronPort-AV: E=McAfee;i="6400,9594,10370"; a="275474996" X-IronPort-AV: E=Sophos;i="5.91,280,1647327600"; d="scan'208";a="275474996" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2022 16:17:20 -0700 X-IronPort-AV: E=Sophos;i="5.91,280,1647327600"; d="scan'208";a="608952580" Received: from nldesimo-desk1.amr.corp.intel.com ([10.7.159.54]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2022 16:17:19 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Sai Chaganty , Michael Kubacki , Heng Luo Subject: [edk2-platforms] [PATCH V2 4/4] TigerlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT Date: Mon, 6 Jun 2022 16:16:45 -0700 Message-Id: <20220606231645.3813-5-nathaniel.l.desimone@intel.com> X-Mailer: git-send-email 2.27.0.windows.1 In-Reply-To: <20220606231645.3813-1-nathaniel.l.desimone@intel.com> References: <20220606231645.3813-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Set the location of the DUTY_CYCLE field in the P_CNT register and indicate the width of the clock duty cycle to OS power management Cc: Sai Chaganty Cc: Michael Kubacki Cc: Heng Luo Signed-off-by: Nate DeSimone --- .../TigerlakeURvp/OpenBoardPkgPcd.dsc | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc index ebbbc7b9f9..aba3c8d6d0 100644 --- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc @@ -1,7 +1,7 @@ ## @file # PCD configuration build description file for the TigerlakeURvp board. # -# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2021 - 2022, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -118,6 +118,14 @@ gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 #!endif gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x40000 + + # + # Set the location of the DUTY_CYCLE field in the P_CNT register + # and indicate the width of the clock duty cycle to OS power management + # + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3 + [PcdsFeatureFlag.common] ###################################### # Edk2 Configuration -- 2.27.0.windows.1