From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f49.google.com (mail-pj1-f49.google.com [209.85.216.49]) by mx.groups.io with SMTP id smtpd.web08.10404.1655328203110502196 for ; Wed, 15 Jun 2022 14:23:23 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@gmail.com header.s=20210112 header.b=nzdjwfYE; spf=pass (domain: gmail.com, ip: 209.85.216.49, mailfrom: taylor.d.beebe@gmail.com) Received: by mail-pj1-f49.google.com with SMTP id v17-20020a17090a899100b001ead067eaf9so3391751pjn.0 for ; Wed, 15 Jun 2022 14:23:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=INMKidJMrrrFJmOrhWpHRUs/2VfxGm+PYZQqpM+aXlc=; b=nzdjwfYEx2DQhldWBWmw+K3Zks0bC3n/CeTVJvbhyZZGDMcjRyH696VpyWH/LXliJ+ dMOcK5mAiHPsgO2iJMDWfVWjY3XL+ctLMMRr04gP0/rgc0eaf/lsWma5eskqEWLjWi8A E1WwZIjH7Ri2bX4uEWnInl4AsCt5QaQwahgK7WdEiSnZKUdj4D7IFbEA6OUMfqcveXHh FkamjF4BLJShYw9kFtzTQZvq6UgyQGCuhVQ3Hhvz3Ut392mX8Unmv7viRUxtjNMNZ1jV AhpsrWgEtLwVs/L2+u5THvwCVsvVpqV5qezmSKEhCsulBfQVu5UqVhjjQZBCucjpIENW K5/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=INMKidJMrrrFJmOrhWpHRUs/2VfxGm+PYZQqpM+aXlc=; b=S9lY8023SDBHsDe+irQoEDwB89o7merJPOzAbZYDiGYXw4zaL3xNeXJN/iCe8CRG71 VGgcIEGvRZ/dkMZSVeBYDK6/6CP4pOjoX/231t4ZbQv902SihHN8i6awgCPy9lLR0NcO e28xXZGzif7mdJ/in1k7y2kJkHqfpN01razcMs4/BeET9Tnjp8FLiwToR2AgGfImD8a5 c+GdILHhIpne7/2qMfSbvvthYs/WtQqizYNqTtOJxSA4Ml3VjSaNFFvjXytaIzVfKaiG la9EIkKYl7QoyHi+jSKvOyqtfjMk9NezHZvN22NcUZLlPGacs9vvQKmFWF8aKLZU7OGT oVlA== X-Gm-Message-State: AJIora9XlnuULIYIre1jkVRom3BHNNrZyRXWw7lgCEoWWf2sAsC0YYaP HYpuh+hRtENqjKuTorRLOK6gPHZXubCFbw== X-Google-Smtp-Source: AGRyM1tMHaGqndu4p83Q3TMG8drxEuhmvrdQicQIwXQ1QszHKg3E8xUmcNc3B2QB+v1Os2UxTtxAAQ== X-Received: by 2002:a17:902:ea93:b0:168:bc83:9ae3 with SMTP id x19-20020a170902ea9300b00168bc839ae3mr1256253plb.123.1655328202200; Wed, 15 Jun 2022 14:23:22 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([50.47.81.182]) by smtp.googlemail.com with ESMTPSA id ep11-20020a17090ae64b00b001eab4d6de9esm7746518pjb.3.2022.06.15.14.23.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jun 2022 14:23:21 -0700 (PDT) From: Taylor Beebe To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar Subject: [PATCH v1 1/1] UefiCpuPkg: CpuDxe: Set RW and P Attributes on Split Pages Date: Wed, 15 Jun 2022 14:23:07 -0700 Message-Id: <20220615212307.1007-2-taylor.d.beebe@gmail.com> X-Mailer: git-send-email 2.36.1.windows.1 In-Reply-To: <20220615212307.1007-1-taylor.d.beebe@gmail.com> References: <20220615212307.1007-1-taylor.d.beebe@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Taylor Beebe A memory range can be submitted for attribute changes which is large enough to not require a page split during the attribute update. Consider the following scenario: 1. An attribute update removed the RW attribute on a range large enough to not require a page split. 2. Later, an attributes update is called to re-add the RW attribute for a subsection of that larger page which requires a split 3. The attribute update logic performs a page split, so now the parent and child pages have matching attributes 4. Then, the attribute update logic changes the child page to have the RW attribute. 5. The child page would then correctly have the RW attribute added but the parent page would still have the RW attribute removed which will cause an improper access violation. The page being split should have loose attributes to accommodate the above case. The split page should always have the attributes set so the lowest level page frame determines the access rights as detailed in 4.10.2.2 of the Intel 64 and IA-32 Architectures Software Developer Manual. Setting the User/Supervisor attribute shouldn't be necessary. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Signed-off-by: Taylor Beebe --- UefiCpuPkg/CpuDxe/CpuPageTable.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c b/UefiCpuPkg/CpuDxe/CpuPageTable.c index f7a4d92e921a..288d9996f6c3 100644 --- a/UefiCpuPkg/CpuDxe/CpuPageTable.c +++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c @@ -38,6 +38,8 @@ #define IA32_PG_NX BIT63 #define PAGE_ATTRIBUTE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_U | IA32_PG_RW | IA32_PG_P) +#define PAGE_ATTRIBUTE_BITS_POST_SPLIT (IA32_PG_RW | IA32_PG_P) + // // Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE // X64 PAE PDPTE does not have such restriction @@ -583,7 +585,7 @@ SplitPage ( NewPageEntry[Index] = (BaseAddress + SIZE_4KB * Index) | AddressEncMask | ((*PageEntry) & PAGE_PROGATE_BITS); } - (*PageEntry) = (UINT64)(UINTN)NewPageEntry | AddressEncMask | ((*PageEntry) & PAGE_ATTRIBUTE_BITS); + (*PageEntry) = (UINT64)(UINTN)NewPageEntry | AddressEncMask | PAGE_ATTRIBUTE_BITS_POST_SPLIT; return RETURN_SUCCESS; } else { return RETURN_UNSUPPORTED; @@ -606,7 +608,7 @@ SplitPage ( NewPageEntry[Index] = (BaseAddress + SIZE_2MB * Index) | AddressEncMask | IA32_PG_PS | ((*PageEntry) & PAGE_PROGATE_BITS); } - (*PageEntry) = (UINT64)(UINTN)NewPageEntry | AddressEncMask | ((*PageEntry) & PAGE_ATTRIBUTE_BITS); + (*PageEntry) = (UINT64)(UINTN)NewPageEntry | AddressEncMask | PAGE_ATTRIBUTE_BITS_POST_SPLIT; return RETURN_SUCCESS; } else { return RETURN_UNSUPPORTED; -- 2.32.0.windows.2