From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mx.groups.io with SMTP id smtpd.web11.17095.1655708906033756111 for ; Mon, 20 Jun 2022 00:08:26 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=GjGcUxqZ; spf=pass (domain: intel.com, ip: 192.55.52.136, mailfrom: heng.luo@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655708906; x=1687244906; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=r7PmpZlEcQ3yXRBZKiX2PeOJ3RAhfXHid2bOWqHoT84=; b=GjGcUxqZR2qr6Lizd7WSCuAvscscdwX4KI17naXB5pKtAFD34LgthQt/ pQp3YJ+9SgqCJPypUoBbranx6ccHNp4CEw2YdW6cgXJ7ifL6V1JOEuzJp IQqu0OL8aFG7DcI22IJPdKZ/8D6eCmJSFyuu2Ji94MVMcAiTT/tydAQnN oe6vyrTtnJbSx7vTcxMpWHFhakI/LTjHP54bcW2+KfNnUj249sOpla7vK dvLGDC1I79/RiFJ/oc3Ha+xmkL6AD+YVCqYYugYN5TYIsTUSOdTnSV4Kz DgO70ve0KWdNpRM51CNrPw04DkiiaDjnWEzPePJ6ks1cJcJfjoe8jI6HS w==; X-IronPort-AV: E=McAfee;i="6400,9594,10380"; a="259645073" X-IronPort-AV: E=Sophos;i="5.92,306,1650956400"; d="scan'208";a="259645073" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2022 00:08:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,306,1650956400"; d="scan'208";a="642977449" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.141]) by fmsmga008.fm.intel.com with ESMTP; 20 Jun 2022 00:08:24 -0700 From: "Heng Luo" To: devel@edk2.groups.io Cc: Ray Ni , Hao Wu Subject: [Patch V2] XhcCreateUsbHc: Check return value of XHC_PAGESIZE_OFFSET Date: Mon, 20 Jun 2022 15:08:16 +0800 Message-Id: <20220620070816.648-1-heng.luo@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3954 Report error if reserved bits are not 0 for PageSize Cc: Ray Ni Cc: Hao Wu Signed-off-by: Heng Luo --- MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c b/MdeModulePkg/Bus/Pci/Xhc= iDxe/Xhci.c index b79499e225..381d7a9536 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c @@ -1,7 +1,7 @@ /** @file=0D The XHCI controller driver.=0D =0D -Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
=0D +Copyright (c) 2011 - 2022, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D @@ -1813,7 +1813,13 @@ XhcCreateUsbHc ( // This xHC supports a page size of 2^(n+12) if bit n is Set. For exampl= e,=0D // if bit 0 is Set, the xHC supports 4k byte page sizes.=0D //=0D - PageSize =3D XhcReadOpReg (Xhc, XHC_PAGESIZE_OFFSET) & XHC_PAGESIZE= _MASK;=0D + PageSize =3D XhcReadOpReg (Xhc, XHC_PAGESIZE_OFFSET);=0D + if ((PageSize & (~XHC_PAGESIZE_MASK)) !=3D 0) {=0D + DEBUG ((DEBUG_ERROR, "XhcCreateUsb3Hc: Reserved bits are not 0 for Pag= eSize\n"));=0D + goto ON_ERROR;=0D + }=0D +=0D + PageSize &=3D XHC_PAGESIZE_MASK;=0D Xhc->PageSize =3D 1 << (HighBitSet32 (PageSize) + 12);=0D =0D ExtCapReg =3D (UINT16)(Xhc->HcCParams.Data.ExtCapReg);=0D --=20 2.31.1.windows.1