* [edk2-platforms][PATCH V4 1/9] Platform/Sgi: Update ACPI version to v6.4
2022-06-27 6:04 [edk2-platforms][PATCH V4 0/9] Upadate the ACPI tables for RD platforms Pranav Madhu
@ 2022-06-27 6:04 ` Pranav Madhu
2022-06-27 6:04 ` [edk2-platforms][PATCH V4 2/9] Platform/Sgi: Update ACPI version to v6.4 for SGI575 platform Pranav Madhu
` (8 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Pranav Madhu @ 2022-06-27 6:04 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar, Pierre Gondois, Thomas Abraham
Update the common ACPI tables used by all the Neoverse Reference Design
platforms to ACPI version v6.4. Significant changes introduced are
update API/macro definitions to incorporate with the extra fields
introduced in ACPI 6.4, such as SPE overflow interrupt number field to
GICC structure of MADT table and adding cache ID field to the cache
structure of PPTT table.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
---
| 252 +++++++++++---------
Platform/ARM/SgiPkg/AcpiTables/Dbg2.aslc | 30 ++-
Platform/ARM/SgiPkg/AcpiTables/Fadt.aslc | 38 +--
Platform/ARM/SgiPkg/AcpiTables/Gtdt.aslc | 69 +++---
Platform/ARM/SgiPkg/AcpiTables/Mcfg.aslc | 26 +-
Platform/ARM/SgiPkg/AcpiTables/Spcr.aslc | 29 ++-
6 files changed, 252 insertions(+), 192 deletions(-)
--git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
index e9b6923cb035..033d398fdb63 100644
--- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
+++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
@@ -1,6 +1,6 @@
/** @file
*
-* Copyright (c) 2018-2021, ARM Limited. All rights reserved.
+* Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -41,136 +41,170 @@
#define OSC_CAP_PLAT_COORDINATED_LPI (1U << 7)
#define OSC_CAP_OS_INITIATED_LPI (1U << 8)
+// Cache type identifier used to calculate unique cache ID for PPTT
+typedef enum {
+ L1DataCache = 1,
+ L1InstructionCache,
+ L2Cache,
+ L3Cache,
+} RD_PPTT_CACHE_TYPE;
+
#pragma pack(1)
// PPTT processor core structure
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Core;
UINT32 ResourceOffset[2];
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE DCache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE ICache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE L2Cache;
} RD_PPTT_CORE;
// PPTT processor cluster structure
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Cluster;
UINT32 ResourceOffset;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE L3Cache;
RD_PPTT_CORE Core[CORE_COUNT];
} RD_PPTT_CLUSTER;
// PPTT processor cluster structure without cache
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Cluster;
RD_PPTT_CORE Core[CORE_COUNT];
} RD_PPTT_MINIMAL_CLUSTER;
// PPTT processor package structure
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Package;
RD_PPTT_MINIMAL_CLUSTER Cluster[CLUSTER_COUNT];
} RD_PPTT_PACKAGE;
#pragma pack ()
//
// PPTT processor structure flags for different SoC components as defined in
-// ACPI 6.3 specification
+// ACPI 6.4 specification
//
// Processor structure flags for SoC package
#define PPTT_PROCESSOR_PACKAGE_FLAGS \
{ \
- EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, \
- EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, \
- EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, \
- EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, \
- EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL \
+ EFI_ACPI_6_4_PPTT_PACKAGE_PHYSICAL, \
+ EFI_ACPI_6_4_PPTT_PROCESSOR_ID_INVALID, \
+ EFI_ACPI_6_4_PPTT_PROCESSOR_IS_NOT_THREAD, \
+ EFI_ACPI_6_4_PPTT_NODE_IS_NOT_LEAF, \
+ EFI_ACPI_6_4_PPTT_IMPLEMENTATION_IDENTICAL \
}
// Processor structure flags for cluster
#define PPTT_PROCESSOR_CLUSTER_FLAGS \
{ \
- EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, \
- EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, \
- EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, \
- EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, \
- EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL \
+ EFI_ACPI_6_4_PPTT_PACKAGE_NOT_PHYSICAL, \
+ EFI_ACPI_6_4_PPTT_PROCESSOR_ID_VALID, \
+ EFI_ACPI_6_4_PPTT_PROCESSOR_IS_NOT_THREAD, \
+ EFI_ACPI_6_4_PPTT_NODE_IS_NOT_LEAF, \
+ EFI_ACPI_6_4_PPTT_IMPLEMENTATION_IDENTICAL \
}
// Processor structure flags for cluster with multi-thread core
#define PPTT_PROCESSOR_CLUSTER_THREADED_FLAGS \
{ \
- EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, \
- EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, \
- EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, \
- EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, \
- EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL \
+ EFI_ACPI_6_4_PPTT_PACKAGE_NOT_PHYSICAL, \
+ EFI_ACPI_6_4_PPTT_PROCESSOR_ID_INVALID, \
+ EFI_ACPI_6_4_PPTT_PROCESSOR_IS_NOT_THREAD, \
+ EFI_ACPI_6_4_PPTT_NODE_IS_NOT_LEAF, \
+ EFI_ACPI_6_4_PPTT_IMPLEMENTATION_IDENTICAL \
}
// Processor structure flags for single-thread core
#define PPTT_PROCESSOR_CORE_FLAGS \
{ \
- EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, \
- EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, \
- EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, \
- EFI_ACPI_6_3_PPTT_NODE_IS_LEAF \
+ EFI_ACPI_6_4_PPTT_PACKAGE_NOT_PHYSICAL, \
+ EFI_ACPI_6_4_PPTT_PROCESSOR_ID_VALID, \
+ EFI_ACPI_6_4_PPTT_PROCESSOR_IS_NOT_THREAD, \
+ EFI_ACPI_6_4_PPTT_NODE_IS_LEAF \
}
// Processor structure flags for multi-thread core
#define PPTT_PROCESSOR_CORE_THREADED_FLAGS \
{ \
- EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, \
- EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, \
- EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, \
- EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, \
- EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL \
+ EFI_ACPI_6_4_PPTT_PACKAGE_NOT_PHYSICAL, \
+ EFI_ACPI_6_4_PPTT_PROCESSOR_ID_INVALID, \
+ EFI_ACPI_6_4_PPTT_PROCESSOR_IS_NOT_THREAD, \
+ EFI_ACPI_6_4_PPTT_NODE_IS_NOT_LEAF, \
+ EFI_ACPI_6_4_PPTT_IMPLEMENTATION_IDENTICAL \
}
// Processor structure flags for CPU thread
#define PPTT_PROCESSOR_THREAD_FLAGS \
{ \
- EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, \
- EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, \
- EFI_ACPI_6_3_PPTT_PROCESSOR_IS_THREAD, \
- EFI_ACPI_6_3_PPTT_NODE_IS_LEAF \
+ EFI_ACPI_6_4_PPTT_PACKAGE_NOT_PHYSICAL, \
+ EFI_ACPI_6_4_PPTT_PROCESSOR_ID_VALID, \
+ EFI_ACPI_6_4_PPTT_PROCESSOR_IS_THREAD, \
+ EFI_ACPI_6_4_PPTT_NODE_IS_LEAF \
}
-// PPTT cache structure flags as defined in ACPI 6.3 Specification
+// PPTT cache structure flags as defined in ACPI 6.4 Specification
#define PPTT_CACHE_STRUCTURE_FLAGS \
{ \
- EFI_ACPI_6_3_PPTT_CACHE_SIZE_VALID, \
- EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_VALID, \
- EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_VALID, \
- EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_VALID, \
- EFI_ACPI_6_3_PPTT_CACHE_TYPE_VALID, \
- EFI_ACPI_6_3_PPTT_WRITE_POLICY_VALID, \
- EFI_ACPI_6_3_PPTT_LINE_SIZE_VALID \
+ EFI_ACPI_6_4_PPTT_CACHE_SIZE_VALID, \
+ EFI_ACPI_6_4_PPTT_NUMBER_OF_SETS_VALID, \
+ EFI_ACPI_6_4_PPTT_ASSOCIATIVITY_VALID, \
+ EFI_ACPI_6_4_PPTT_ALLOCATION_TYPE_VALID, \
+ EFI_ACPI_6_4_PPTT_CACHE_TYPE_VALID, \
+ EFI_ACPI_6_4_PPTT_WRITE_POLICY_VALID, \
+ EFI_ACPI_6_4_PPTT_LINE_SIZE_VALID, \
+ EFI_ACPI_6_4_PPTT_CACHE_ID_VALID \
}
// PPTT cache attributes for data cache
#define PPTT_DATA_CACHE_ATTR \
{ \
- EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
- EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \
- EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK \
+ EFI_ACPI_6_4_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
+ EFI_ACPI_6_4_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \
+ EFI_ACPI_6_4_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK \
}
// PPTT cache attributes for instruction cache
#define PPTT_INST_CACHE_ATTR \
{ \
- EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, \
- EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \
- EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK \
+ EFI_ACPI_6_4_CACHE_ATTRIBUTES_ALLOCATION_READ, \
+ EFI_ACPI_6_4_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \
+ EFI_ACPI_6_4_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK \
}
// PPTT cache attributes for unified cache
#define PPTT_UNIFIED_CACHE_ATTR \
{ \
- EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
- EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \
- EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK \
+ EFI_ACPI_6_4_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
+ EFI_ACPI_6_4_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \
+ EFI_ACPI_6_4_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK \
}
+/** Helper macro to calculate a unique cache ID
+
+ Macro to calculate a unique 32 bit cache ID. The 32-bit encoding format of the
+ cache ID is
+ * Bits[31:24]: Unused
+ * Bits[23:20]: Package number the cache belongs to
+ * Bits[19:12]: Cluster number the cache belongs to (0, if not a cluster cache)
+ * Bits[11:4] : Core number the cache belongs to (0, if not a CPU cache)
+ * Bits[3:0] : Cache Type (as defined by RD_PPTT_CACHE_TYPE)
+
+ Note: Cache ID zero is invalid as per ACPI 6.4 specification. Also this
+ calculation is not based on any specification.
+
+ @param [in] PackageId Package instance number.
+ @param [in] ClusterId Cluster instance number (for Cluster cache, 0 otherwise)
+ @param [in] CpuId CPU instance number (for CPU cache, 0 otherwise).
+ @param [in] CacheType Identifier for cache type as defined by
+ RD_PPTT_CACHE_TYPE.
+**/
+#define RD_PPTT_CACHE_ID(PackageId, ClusterId, CoreId, CacheType) \
+ ( \
+ (((PackageId) & 0xF) << 20) | (((ClusterId) & 0xFF) << 12) | \
+ (((CoreId) & 0xFF) << 4) | ((CacheType) & 0xF) \
+ )
+
// A macro to initialise the common header part of EFI ACPI tables as defined by
// EFI_ACPI_DESCRIPTION_HEADER structure.
#define ARM_ACPI_HEADER(Signature, Type, Revision) { \
@@ -185,12 +219,13 @@ typedef struct {
EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \
}
-// EFI_ACPI_6_2_GIC_STRUCTURE
-#define EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, \
- PmuIrq, GicBase, GicVBase, GicHBase, GsivId, GicRBase, Efficiency) \
+// EFI_ACPI_6_4_GIC_STRUCTURE
+#define EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, \
+ PmuIrq, GicBase, GicVBase, GicHBase, GsivId, GicRBase, Efficiency, \
+ SpeOverflowInterrupt) \
{ \
- EFI_ACPI_6_2_GIC, /* Type */ \
- sizeof (EFI_ACPI_6_2_GIC_STRUCTURE), /* Length */ \
+ EFI_ACPI_6_4_GIC, /* Type */ \
+ sizeof (EFI_ACPI_6_4_GIC_STRUCTURE), /* Length */ \
EFI_ACPI_RESERVED_WORD, /* Reserved */ \
GicId, /* CPUInterfaceNumber */ \
AcpiCpuUid, /* AcpiProcessorUid */ \
@@ -205,19 +240,16 @@ typedef struct {
GicRBase, /* GICRBaseAddress */ \
Mpidr, /* MPIDR */ \
Efficiency, /* ProcessorPowerEfficiencyClass */ \
- { \
- EFI_ACPI_RESERVED_BYTE, /* Reserved2[0] */ \
- EFI_ACPI_RESERVED_BYTE, /* Reserved2[1] */ \
- EFI_ACPI_RESERVED_BYTE /* Reserved2[2] */ \
- } \
+ EFI_ACPI_RESERVED_BYTE, /* Reserved2 */ \
+ SpeOverflowInterrupt /* SpeOverflowInterrupt */ \
}
-// EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE
-#define EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(GicDistHwId, GicDistBase, \
+// EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE
+#define EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(GicDistHwId, GicDistBase, \
GicDistVector, GicVersion) \
{ \
- EFI_ACPI_6_2_GICD, /* Type */ \
- sizeof (EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE), \
+ EFI_ACPI_6_4_GICD, /* Type */ \
+ sizeof (EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE), \
EFI_ACPI_RESERVED_WORD, /* Reserved1 */ \
GicDistHwId, /* GicId */ \
GicDistBase, /* PhysicalBaseAddress */ \
@@ -230,43 +262,43 @@ typedef struct {
} \
}
-// EFI_ACPI_6_2_GICR_STRUCTURE
-#define EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(RedisRegionAddr, RedisDiscLength) \
+// EFI_ACPI_6_4_GICR_STRUCTURE
+#define EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(RedisRegionAddr, RedisDiscLength) \
{ \
- EFI_ACPI_6_2_GICR, /* Type */ \
- sizeof (EFI_ACPI_6_2_GICR_STRUCTURE), /* Length */ \
+ EFI_ACPI_6_4_GICR, /* Type */ \
+ sizeof (EFI_ACPI_6_4_GICR_STRUCTURE), /* Length */ \
EFI_ACPI_RESERVED_WORD, /* Reserved */ \
RedisRegionAddr, /* DiscoveryRangeBaseAddress */ \
RedisDiscLength /* DiscoveryRangeLength */ \
}
-// EFI_ACPI_6_2_GIC_ITS_STRUCTURE
-#define EFI_ACPI_6_2_GIC_ITS_INIT(GicItsId, GicItsBase) \
+// EFI_ACPI_6_4_GIC_ITS_STRUCTURE
+#define EFI_ACPI_6_4_GIC_ITS_INIT(GicItsId, GicItsBase) \
{ \
- EFI_ACPI_6_2_GIC_ITS, /* Type */ \
- sizeof (EFI_ACPI_6_2_GIC_ITS_STRUCTURE), \
+ EFI_ACPI_6_4_GIC_ITS, /* Type */ \
+ sizeof (EFI_ACPI_6_4_GIC_ITS_STRUCTURE), \
EFI_ACPI_RESERVED_WORD, /* Reserved */ \
GicItsId, /* GicItsId */ \
GicItsBase, /* PhysicalBaseAddress */ \
EFI_ACPI_RESERVED_DWORD /* DiscoveryRangeLength */ \
}
-// EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE
-#define EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT( \
+// EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE
+#define EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT( \
ProximityDomain, Base, Length, Flags) \
{ \
- 1, sizeof (EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE), ProximityDomain, \
+ 1, sizeof (EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE), ProximityDomain, \
EFI_ACPI_RESERVED_WORD, (Base) & 0xffffffff, \
(Base) >> 32, (Length) & 0xffffffff, \
(Length) >> 32, EFI_ACPI_RESERVED_DWORD, Flags, \
EFI_ACPI_RESERVED_QWORD \
}
-// EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE
-#define EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT( \
+// EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE
+#define EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT( \
ProximityDomain, ACPIProcessorUID, Flags, ClockDomain) \
{ \
- 3, sizeof (EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE), ProximityDomain, \
+ 3, sizeof (EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE), ProximityDomain, \
ACPIProcessorUID, Flags, ClockDomain \
}
@@ -274,16 +306,16 @@ typedef struct {
// HMAT related structures
//
// Memory Proximity Domain Attributes Structure
-// Refer Section 5.2.27.3 in ACPI Specification, Version 6.3
-#define EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT( \
+// Refer Section 5.2.27.3 in ACPI Specification, Version 6.4
+#define EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT( \
Flags, ProximityDomainForAttachedIntiator, ProximityDomainForMemory) \
{ \
- EFI_ACPI_6_3_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES, \
+ EFI_ACPI_6_4_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES, \
{ \
EFI_ACPI_RESERVED_BYTE, \
EFI_ACPI_RESERVED_BYTE \
}, \
- sizeof (EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES), \
+ sizeof (EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES), \
{ \
Flags, \
0 \
@@ -319,28 +351,27 @@ typedef struct {
}
// System Locality Latency and Bandwidth Information Structure
-// Refer Section 5.2.27.4 in ACPI Specification, Version 6.3
-#define EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT( \
- Flags, DataType, NumInitiatorProximityDomains, \
+// Refer Section 5.2.27.4 in ACPI Specification, Version 6.4
+#define EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT( \
+ Flags, DataType, MinTransferSize, NumInitiatorProximityDomains, \
NumTargetProximityDomains, EntryBaseUnit) \
{ \
- EFI_ACPI_6_3_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO, \
+ EFI_ACPI_6_4_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO, \
{ \
EFI_ACPI_RESERVED_BYTE, \
EFI_ACPI_RESERVED_BYTE \
}, \
- sizeof (EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO) + \
+ sizeof (EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO) + \
(4 * NumInitiatorProximityDomains) + (4 * NumTargetProximityDomains) + \
(2 * NumInitiatorProximityDomains * NumTargetProximityDomains), \
{ \
Flags, \
+ 0, \
0 \
}, \
+ MinTransferSize, \
DataType, \
- { \
- EFI_ACPI_RESERVED_BYTE, \
- EFI_ACPI_RESERVED_BYTE \
- }, \
+ EFI_ACPI_RESERVED_BYTE, \
NumInitiatorProximityDomains, \
NumTargetProximityDomains, \
{ \
@@ -353,17 +384,17 @@ typedef struct {
}
// Memory Side Cache Information Structure
-// Refer Section 5.2.27.5 in ACPI Specification, Version 6.3
-#define EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT( \
+// Refer Section 5.2.27.5 in ACPI Specification, Version 6.4
+#define EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT( \
MemoryProximityDomain, MemorySideCacheSize, CacheAttributes, \
NumberOfSmbiosHandles) \
{ \
- EFI_ACPI_6_3_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO, \
+ EFI_ACPI_6_4_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO, \
{ \
EFI_ACPI_RESERVED_BYTE, \
EFI_ACPI_RESERVED_BYTE \
}, \
- sizeof (EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO) + \
+ sizeof (EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO) + \
(NumberOfSmbiosHandles * 2), \
MemoryProximityDomain, \
{ \
@@ -382,7 +413,7 @@ typedef struct {
}
/** A macro to initialise the Memory Side Cache Information Attributes.
- See Table 5.124 in ACPI Specification, Version 6.3
+ See Table 5.130 in ACPI Specification, Version 6.4
@param [in] TotalCacheLevels Total Cache Levels for this Memory Proximity.
@param [in] CacheLevel Cache Level described in this structure.
@@ -397,11 +428,11 @@ typedef struct {
TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLineSize \
}
-// EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR
-#define EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT(Length, Flag, Parent, \
+// EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR
+#define EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT(Length, Flag, Parent, \
ACPIProcessorID, NumberOfPrivateResource) \
{ \
- EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, /* Type 0 */ \
+ EFI_ACPI_6_4_PPTT_TYPE_PROCESSOR, /* Type 0 */ \
Length, /* Length */ \
{ \
EFI_ACPI_RESERVED_BYTE, \
@@ -413,12 +444,12 @@ typedef struct {
NumberOfPrivateResource /* Resource count */ \
}
-// EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE
-#define EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT(Flag, NextLevelCache, Size, \
- NoOfSets, Associativity, Attributes, LineSize) \
+// EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE
+#define EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT(Flag, NextLevelCache, Size, \
+ NoOfSets, Associativity, Attributes, LineSize, CacheId) \
{ \
- EFI_ACPI_6_3_PPTT_TYPE_CACHE, /* Type 1 */ \
- sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), /* Length */ \
+ EFI_ACPI_6_4_PPTT_TYPE_CACHE, /* Type 1 */ \
+ sizeof (EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE), /* Length */ \
{ \
EFI_ACPI_RESERVED_BYTE, \
EFI_ACPI_RESERVED_BYTE, \
@@ -429,7 +460,8 @@ typedef struct {
NoOfSets, /* Num of sets */ \
Associativity, /* Num of ways */ \
Attributes, /* Cache attributes */ \
- LineSize /* Line size in bytes */ \
+ LineSize, /* Line size in bytes */ \
+ CacheId /* Cache id */ \
}
/** Helper macro for CPPC _CPC object initialization. Use of this macro is
diff --git a/Platform/ARM/SgiPkg/AcpiTables/Dbg2.aslc b/Platform/ARM/SgiPkg/AcpiTables/Dbg2.aslc
index 279f847cce4c..b85e7272fd82 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Dbg2.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/Dbg2.aslc
@@ -1,16 +1,22 @@
/** @file
-* Debug Port Table 2 (DBG2)
-*
-* Copyright (c) 2018, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Debug Port Table 2 (DBPG2)
+
+ Debug Port Table 2 is used in platform firmware to describe the debug
+ ports available on the system to the OS. The reference design platforms use
+ the non-secure UART port in the compute subsystem as the debug port.
+
+ Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup
+ /acpi-debug-port-table
**/
-#include "SgiAcpiHeader.h"
-#include <Library/AcpiLib.h>
-#include <IndustryStandard/Acpi62.h>
#include <IndustryStandard/DebugPort2Table.h>
+#include <Library/AcpiLib.h>
+#include "SgiAcpiHeader.h"
#define SGI_DBG2_NUM_DEBUG_PORTS 1
#define SGI_DBG2_NUM_GAS 1
@@ -21,7 +27,7 @@
typedef struct {
EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device;
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister;
UINT32 AddressSize;
UINT8 NameSpaceString[SGI_DBG2_NS_STR_LENGTH];
} DBG2_DEBUG_DEVICE_INFORMATION;
@@ -48,7 +54,7 @@ typedef struct {
OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister), /* UINT16 BaseAddressRegister Offset */ \
OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize) /* UINT16 AddressSize Offset */ \
}, \
- ARM_GAS32 (UartBase), /* EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister */ \
+ ARM_GAS32 (UartBase), /* EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister */ \
UartAddrLen, /* UINT32 AddressSize */ \
UartNameStr /* UINT8 NameSpaceString[MAX_DBG2_NAME_LEN] */ \
}
@@ -56,7 +62,7 @@ typedef struct {
STATIC DBG2_TABLE Dbg2 = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_DEBUG_PORT_2_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_DEBUG_PORT_2_TABLE_SIGNATURE,
DBG2_TABLE,
EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION
),
diff --git a/Platform/ARM/SgiPkg/AcpiTables/Fadt.aslc b/Platform/ARM/SgiPkg/AcpiTables/Fadt.aslc
index 9472aff2e054..5ad448d9c9d2 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Fadt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/Fadt.aslc
@@ -1,26 +1,32 @@
/** @file
-* Fixed ACPI Description Table (FADT)
-*
-* Copyright (c) 2018, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Fixed ACPI Description Table (FADT)
+
+ FADT defines various fixed hardware ACPI information vital to an ACPI
+ compatible OS. FADT also has a pointer to the DSDT that contains the
+ Differentiated Definition Block, which in turn provides variable information
+ to an ACPI-compatible OS concerning the base system design.
+
+ Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.9, Fixed ACPI Description Table
**/
-#include "SgiAcpiHeader.h"
#include <Library/AcpiLib.h>
-#include <IndustryStandard/Acpi.h>
+#include "SgiAcpiHeader.h"
-STATIC EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
+STATIC EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
),
0, // UINT32 FirmwareCtrl
0, // UINT32 Dsdt
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
- EFI_ACPI_6_2_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmProfile
+ EFI_ACPI_6_4_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmProfile
0, // UINT16 SciInt
0, // UINT32 SmiCmd
0, // UINT8 AcpiEnable
@@ -54,11 +60,11 @@ STATIC EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
0, // UINT8 Century
0, // UINT16 IaPcBootArch
0, // UINT8 Reserved1
- EFI_ACPI_6_2_HW_REDUCED_ACPI | EFI_ACPI_6_2_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags
+ EFI_ACPI_6_4_HW_REDUCED_ACPI | EFI_ACPI_6_4_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags
NULL_GAS, // GAS ResetReg
0, // UINT8 ResetValue
- EFI_ACPI_6_2_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags
- EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision
+ EFI_ACPI_6_4_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags
+ EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision
0, // UINT64 XFirmwareCtrl
0, // UINT64 XDsdt
NULL_GAS, // GAS XPm1aEvtBlk
diff --git a/Platform/ARM/SgiPkg/AcpiTables/Gtdt.aslc b/Platform/ARM/SgiPkg/AcpiTables/Gtdt.aslc
index b53cbb228f92..70765f87e537 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Gtdt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/Gtdt.aslc
@@ -1,16 +1,21 @@
/** @file
-* Generic Timer Description Table (GTDT)
-*
-* Copyright (c) 2018, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Generic Timer Description Table (GTDT)
+
+ GTDT provides OSPM with information about a system’s Generic Timers
+ configuration. This table lists the watchdog and generic timer instances
+ available on the reference design platforms.
+
+ Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.24, Generic Timer Description Table
**/
-#include "SgiAcpiHeader.h"
#include <Library/AcpiLib.h>
#include <Library/PcdLib.h>
-#include <IndustryStandard/Acpi62.h>
+#include "SgiAcpiHeader.h"
#define SGI_PLATFORM_WATCHDOG_COUNT 2
#define SGI_PLATFORM_TIMER_COUNT (SGI_PLATFORM_WATCHDOG_COUNT + 1)
@@ -18,7 +23,7 @@
#define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF
#define GTDT_GLOBAL_FLAGS 0
-#define GTDT_GTIMER_FLAGS EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTDT_GTIMER_FLAGS EFI_ACPI_6_4_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
#define SGI_GT_BLOCK_CTL_BASE 0x2A810000
#define SGI_GT_BLOCK_FRAME1_CTL_BASE 0x2A820000
@@ -30,18 +35,18 @@
#define SGI_GT_BLOCK_FRAME0_GSIV FixedPcdGet32 (PcdGtFrame0Gsiv)
#define SGI_GTX_TIMER_FLAGS 0
-#define GTX_TIMER_SECURE EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER
+#define GTX_TIMER_SECURE EFI_ACPI_6_4_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER
#define GTX_TIMER_NON_SECURE 0
-#define GTX_TIMER_SAVE_CONTEXT EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY
+#define GTX_TIMER_SAVE_CONTEXT EFI_ACPI_6_4_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY
#define SGI_GTX_COMMON_FLAGS_S (GTX_TIMER_SAVE_CONTEXT | GTX_TIMER_SECURE)
#define SGI_GTX_COMMON_FLAGS_NS (GTX_TIMER_SAVE_CONTEXT | GTX_TIMER_NON_SECURE)
-#define EFI_ACPI_6_2_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( \
+#define EFI_ACPI_6_4_ARM_GENERIC_WATCHDOG_STRUCTURE_INIT( \
RefreshFramePhysicalAddress, ControlFramePhysicalAddress, \
WatchdogTimerGSIV, WatchdogTimerFlags) \
{ \
- EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG, \
- sizeof (EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE), \
+ EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG, \
+ sizeof (EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_STRUCTURE), \
EFI_ACPI_RESERVED_WORD, \
RefreshFramePhysicalAddress, \
ControlFramePhysicalAddress, \
@@ -52,20 +57,20 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
- EFI_ACPI_6_2_GTDT_GT_BLOCK_STRUCTURE GtBlock;
- EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_STRUCTURE Frames[SGI_TIMER_FRAMES_COUNT];
- EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[SGI_PLATFORM_WATCHDOG_COUNT];
-} EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLES;
+ EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
+ EFI_ACPI_6_4_GTDT_GT_BLOCK_STRUCTURE GtBlock;
+ EFI_ACPI_6_4_GTDT_GT_BLOCK_TIMER_STRUCTURE Frames[SGI_TIMER_FRAMES_COUNT];
+ EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_STRUCTURE Watchdogs[SGI_PLATFORM_WATCHDOG_COUNT];
+} EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLES;
#pragma pack ()
-STATIC EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
+STATIC EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLES,
- EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLES,
+ EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
),
SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
0, // UINT32 Reserved
@@ -79,17 +84,19 @@ STATIC EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags
0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress
SGI_PLATFORM_TIMER_COUNT, // UINT32 PlatformTimerCount
- sizeof (EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
+ sizeof (EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLE), // UINT32 PlatfromTimerOffset
+ 0, // UINT32 VirtualPL2TimerGSIV
+ 0 // UINT32 VirtualPL2TimerFlags
},
{
- EFI_ACPI_6_2_GTDT_GT_BLOCK, // UINT8 Type
- sizeof (EFI_ACPI_6_2_GTDT_GT_BLOCK_STRUCTURE) + // UINT16 Length
- sizeof (EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_STRUCTURE) *
+ EFI_ACPI_6_4_GTDT_GT_BLOCK, // UINT8 Type
+ sizeof (EFI_ACPI_6_4_GTDT_GT_BLOCK_STRUCTURE) + // UINT16 Length
+ sizeof (EFI_ACPI_6_4_GTDT_GT_BLOCK_TIMER_STRUCTURE) *
SGI_TIMER_FRAMES_COUNT,
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved
SGI_GT_BLOCK_CTL_BASE, // UINT64 CntCtlBase
SGI_TIMER_FRAMES_COUNT, // UINT32 GTBlockTimerCount
- sizeof (EFI_ACPI_6_2_GTDT_GT_BLOCK_STRUCTURE) // UINT32 GTBlockTimerOffset
+ sizeof (EFI_ACPI_6_4_GTDT_GT_BLOCK_STRUCTURE) // UINT32 GTBlockTimerOffset
},
{
{
@@ -124,17 +131,17 @@ STATIC EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
}
},
{
- EFI_ACPI_6_2_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT (
+ EFI_ACPI_6_4_ARM_GENERIC_WATCHDOG_STRUCTURE_INIT (
FixedPcdGet32 (PcdGenericWatchdogRefreshBase),
FixedPcdGet32 (PcdGenericWatchdogControlBase),
FixedPcdGet32 (PcdWdogWS0Gsiv),
0
),
- EFI_ACPI_6_2_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT (
+ EFI_ACPI_6_4_ARM_GENERIC_WATCHDOG_STRUCTURE_INIT (
FixedPcdGet32 (PcdGenericWatchdogRefreshBase),
FixedPcdGet32 (PcdGenericWatchdogControlBase),
FixedPcdGet32 (PcdWdogWS1Gsiv),
- EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER
+ EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_FLAG_SECURE_TIMER
)
}
};
diff --git a/Platform/ARM/SgiPkg/AcpiTables/Mcfg.aslc b/Platform/ARM/SgiPkg/AcpiTables/Mcfg.aslc
index 090297d9541a..96fb6281ea53 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Mcfg.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/Mcfg.aslc
@@ -1,22 +1,24 @@
/** @file
-* Memory mapped configuration space base address description table (MCFG)
-*
-* Copyright (c) 2018, ARM Ltd. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Memory mapped configuration space base address description table (MCFG)
+
+ The MCFG table provides the address of the PCI configuration space, which
+ is required by the OS to perform the PCIe bus enumeration.
+
+ Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - http://www.pcisig.com/home
**/
-#include <IndustryStandard/Acpi62.h>
#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
#include "SgiAcpiHeader.h"
#include "SgiPlatform.h"
-#include <Library/AcpiLib.h>
-#include <Library/ArmLib.h>
-#include <IndustryStandard/Acpi.h>
-
#pragma pack(1)
typedef struct
{
@@ -28,7 +30,7 @@ typedef struct
EFI_ACPI_PCI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
EFI_ACPI_PCI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE,
EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION
),
diff --git a/Platform/ARM/SgiPkg/AcpiTables/Spcr.aslc b/Platform/ARM/SgiPkg/AcpiTables/Spcr.aslc
index 632144530076..6467fcdf4fd0 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Spcr.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/Spcr.aslc
@@ -1,20 +1,27 @@
/** @file
-* Serial Port Console Redirection Table (SPCR)
-*
-* Copyright (c) 2018, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Serial Port Console Redirection Table (SPCR)
+
+ SPCR table provides information about the configuration and use of the serial
+ port or non-legacy UART interface. This table list the non-secure UART
+ instance in the compute subsystem on the reference design platforms as the
+ available serial port.
+
+ Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - https://docs.microsoft.com/en-us/windows-hardware/drivers/serports/
+ serial-port-console-redirection-table
**/
-#include "SgiAcpiHeader.h"
-#include <Library/AcpiLib.h>
-#include <IndustryStandard/Acpi62.h>
#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+#include <Library/AcpiLib.h>
+#include "SgiAcpiHeader.h"
STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION
),
@@ -26,7 +33,7 @@ STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE
},
- // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE BaseAddress;
+ // EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE BaseAddress;
ARM_GAS32 (FixedPcdGet64 (PcdSerialDbgRegisterBase)),
// UINT8 InterruptType;
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC,
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [edk2-platforms][PATCH V4 2/9] Platform/Sgi: Update ACPI version to v6.4 for SGI575 platform
2022-06-27 6:04 [edk2-platforms][PATCH V4 0/9] Upadate the ACPI tables for RD platforms Pranav Madhu
2022-06-27 6:04 ` [edk2-platforms][PATCH V4 1/9] Platform/Sgi: Update ACPI version to v6.4 Pranav Madhu
@ 2022-06-27 6:04 ` Pranav Madhu
2022-06-27 6:04 ` [edk2-platforms][PATCH V4 3/9] Platform/Sgi: Update ACPI version to v6.4 for RD-N1-Edge platform Pranav Madhu
` (7 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Pranav Madhu @ 2022-06-27 6:04 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar, Pierre Gondois, Thomas Abraham
Update the SGI575 platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc | 105 +++++++++++---------
Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc | 87 ++++++++--------
2 files changed, 101 insertions(+), 91 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc
index f04b77929d71..d3d7d946655f 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2018, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the GIC
+ CPU interface, redistributor, distributor and ITS blocks on the SGI-575
+ platform is included in this table.
+
+ Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
-#include <IndustryStandard/Acpi.h>
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORES (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -21,75 +27,76 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORES];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts;
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CORES];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTURE GicIts;
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0, // Flags
},
{
- // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
+ // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
- // Efficiency)
+ // Efficiency,
+ // SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
- // (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ // (see note in 5.2.12.14 GICC Structure of ACPI v6.4).
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-1
- 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-1
+ 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-2
- 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-2
+ 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-3
- 0, 3, GET_MPID(0x0, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-3
+ 0, 3, GET_MPID(0x0, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-4
- 0, 4, GET_MPID(0x100, 0x00), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-4
+ 0, 4, GET_MPID(0x100, 0x00), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-5
- 0, 5, GET_MPID(0x100, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-5
+ 0, 5, GET_MPID(0x100, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-6
- 0, 6, GET_MPID(0x100, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-6
+ 0, 6, GET_MPID(0x100, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-7
- 0, 7, GET_MPID(0x100, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-7
+ 0, 7, GET_MPID(0x100, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
},
// GIC Distributor Entry
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
0, 3),
// GIC Redistributor
- EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
+ EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
SIZE_1MB),
// GIC ITS
- EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(0, 0x30040000),
};
//
diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc
index a1b351379c9e..e1a4a500ebd3 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc
@@ -1,27 +1,25 @@
/** @file
-* Processor Properties Topology Table (PPTT) for SGI-575 platform
-*
-* This file describes the topological structure of the processor block on the
-* SGI-575 platform in the form as defined by ACPI PPTT table. The SGI-575
-* platform includes two clusters with four single-thread CPUS. Each of the CPUs
-* include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache.
-* Each cluster includes a 2MB L3 cache.
-*
-* Copyright (c) 2021, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-* @par Specification Reference:
-* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+ Processor Properties Topology Table (PPTT) for SGI-575 platform
+
+ This file describes the topological structure of the processor block on the
+ SGI-575 platform in the form as defined by ACPI PPTT table. The SGI-575
+ platform includes two clusters with four single-thread CPUS. Each of the CPUs
+ include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache.
+ Each cluster includes a 2MB L3 cache.
+
+ Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology Table
**/
-#include <IndustryStandard/Acpi.h>
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
-
-#include "SgiPlatform.h"
#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
/** Define helper macro for populating processor core information.
@@ -32,10 +30,10 @@
#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) \
{ \
/* Parameters for CPU Core */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \
PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId]), /* Parent */ \
((PackageId << 3) | (ClusterId << 2) | CpuId), /* ACPI Id */ \
2 /* Num of private resource */ \
@@ -43,47 +41,51 @@
\
/* Offsets of the private resources */ \
{ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].DCache), \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].ICache) \
}, \
\
/* L1 data cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
/* Next level of cache */ \
SIZE_64KB, /* Size */ \
64, /* Num of sets */ \
16, /* Associativity */ \
PPTT_DATA_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1DataCache) /* Cache id */\
), \
\
/* L1 instruction cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
/* Next level of cache */ \
SIZE_64KB, /* Size */ \
256, /* Num of sets */ \
4, /* Associativity */ \
PPTT_INST_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1InstructionCache) \
+ /* Cache id */ \
), \
\
/* L2 cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
0, /* Next level of cache */ \
SIZE_512KB, /* Size */ \
1024, /* Num of sets */ \
8, /* Associativity */ \
PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L2Cache) /* Cache id */ \
), \
}
@@ -95,29 +97,30 @@
#define PPTT_CLUSTER_INIT(PackageId, ClusterId) \
{ \
/* Parameters for Cluster */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
OFFSET_OF (RD_PPTT_CLUSTER, L3Cache), \
/* Length */ \
PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package), /* Parent */ \
((PackageId << 1) | ClusterId), /* ACPI Id */ \
1 /* Num of private resource */ \
), \
\
/* Offsets of the private resources */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].L3Cache), \
\
/* L3 cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
0, /* Next level of cache */ \
SIZE_2MB, /* Size */ \
2048, /* Num of sets */ \
16, /* Associativity */ \
PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, 0, L3Cache) /* Cache id */ \
), \
\
/* Initialize child cores */ \
@@ -131,7 +134,7 @@
#pragma pack(1)
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Package;
RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT];
} SGI575_PPTT_PACKAGE;
@@ -139,22 +142,22 @@ typedef struct {
* Processor Properties Topology Table
*/
typedef struct {
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
SGI575_PPTT_PACKAGE Package;
-} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
)
},
{
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT (
OFFSET_OF (SGI575_PPTT_PACKAGE, Cluster[0]),
PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0
),
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [edk2-platforms][PATCH V4 3/9] Platform/Sgi: Update ACPI version to v6.4 for RD-N1-Edge platform
2022-06-27 6:04 [edk2-platforms][PATCH V4 0/9] Upadate the ACPI tables for RD platforms Pranav Madhu
2022-06-27 6:04 ` [edk2-platforms][PATCH V4 1/9] Platform/Sgi: Update ACPI version to v6.4 Pranav Madhu
2022-06-27 6:04 ` [edk2-platforms][PATCH V4 2/9] Platform/Sgi: Update ACPI version to v6.4 for SGI575 platform Pranav Madhu
@ 2022-06-27 6:04 ` Pranav Madhu
2022-06-27 6:04 ` [edk2-platforms][PATCH V4 4/9] Platform/Sgi: Update ACPI version to v6.4 for RD-N1-Edge-X2 platform Pranav Madhu
` (6 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Pranav Madhu @ 2022-06-27 6:04 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar, Pierre Gondois, Thomas Abraham
Update the RD-N1-Edge platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc | 105 +++++++++++---------
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 91 +++++++++--------
2 files changed, 104 insertions(+), 92 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
index 05eb78c5616a..df2576e1d9b7 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-N1-Edge
+ platform is included in this table.
+
+ Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
-#include <IndustryStandard/Acpi.h>
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -21,75 +27,76 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts;
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTURE GicIts;
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
- // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
+ // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
- // Efficiency)
+ // Efficiency,
+ // SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
- // (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ // (see note in 5.2.12.14 GICC Structure of ACPI v6.4).
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-1
- 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-1
+ 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-2
- 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-2
+ 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-3
- 0, 3, GET_MPID(0x0, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-3
+ 0, 3, GET_MPID(0x0, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-4
- 0, 4, GET_MPID(0x100, 0x00), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-4
+ 0, 4, GET_MPID(0x100, 0x00), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-5
- 0, 5, GET_MPID(0x100, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-5
+ 0, 5, GET_MPID(0x100, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-6
- 0, 6, GET_MPID(0x100, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-6
+ 0, 6, GET_MPID(0x100, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-7
- 0, 7, GET_MPID(0x100, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-7
+ 0, 7, GET_MPID(0x100, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */)
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0)
},
// GIC Distributor Entry
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
0, 3),
// GIC Redistributor
- EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
+ EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
SIZE_1MB),
// GIC ITS
- EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000)
+ EFI_ACPI_6_4_GIC_ITS_INIT(0, 0x30040000)
};
//
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc
index 923ee9014970..917d50914224 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc
@@ -1,28 +1,26 @@
/** @file
-* Processor Properties Topology Table (PPTT) for RD-N1-Edge single-chip platform
-*
-* This file describes the topological structure of the processor block on the
-* RD-N1-Edge single-chip platform in the form as defined by ACPI PPTT table. The
-* RD-N1-Edge platform includes two clusters with four single-thread CPUS. Each
-* of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2
-* cache. Each cluster includes a 2MB L3 cache. The platform also includes a
-* system level cache of 8MB.
-*
-* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-* @par Specification Reference:
-* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+ Processor Properties Topology Table (PPTT) for RD-N1-Edge single-chip platform
+
+ This file describes the topological structure of the processor block on the
+ RD-N1-Edge single-chip platform in the form as defined by ACPI PPTT table. The
+ RD-N1-Edge platform includes two clusters with four single-thread CPUS. Each
+ of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2
+ cache. Each cluster includes a 2MB L3 cache. The platform also includes a
+ system level cache of 8MB.
+
+ Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology Table
**/
-#include <IndustryStandard/Acpi.h>
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
-
-#include "SgiPlatform.h"
#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
/** Define helper macro for populating processor core information.
@@ -33,10 +31,10 @@
#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) \
{ \
/* Parameters for CPU Core */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \
PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId]), /* Parent */ \
((PackageId << 3) | (ClusterId << 2) | CpuId), /* ACPI Id */ \
2 /* Num of private resource */ \
@@ -44,47 +42,53 @@
\
/* Offsets of the private resources */ \
{ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].DCache), \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].ICache) \
}, \
\
/* L1 data cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
/* Next level of cache */ \
SIZE_64KB, /* Size */ \
256, /* Num of sets */ \
4, /* Associativity */ \
PPTT_DATA_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1DataCache) \
+ /* Cache id */ \
), \
\
/* L1 instruction cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
/* Next level of cache */ \
SIZE_64KB, /* Size */ \
256, /* Num of sets */ \
4, /* Associativity */ \
PPTT_INST_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1InstructionCache) \
+ /* Cache id */ \
), \
\
/* L2 cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
0, /* Next level of cache */ \
SIZE_512KB, /* Size */ \
1024, /* Num of sets */ \
8, /* Associativity */ \
PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L2Cache) \
+ /* Cache id */ \
), \
}
@@ -96,28 +100,29 @@
#define PPTT_CLUSTER_INIT(PackageId, ClusterId) \
{ \
/* Parameters for Cluster */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
OFFSET_OF (RD_PPTT_CLUSTER, L3Cache), /* Length */ \
PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package), /* Parent */ \
((PackageId << 1) | ClusterId), /* ACPI Id */ \
1 /* Num of private resource */ \
), \
\
/* Offsets of the private resources */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].L3Cache), \
\
/* L3 cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
0, /* Next level of cache */ \
SIZE_2MB, /* Size */ \
2048, /* Num of sets */ \
16, /* Associativity */ \
PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, 0, L3Cache) /* Cache id */ \
), \
\
/* Initialize child cores */ \
@@ -131,7 +136,7 @@
#pragma pack(1)
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Package;
RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT];
} RDN1EDGE_PPTT_PACKAGE ;
@@ -139,22 +144,22 @@ typedef struct {
* Processor Properties Topology Table
*/
typedef struct {
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
RDN1EDGE_PPTT_PACKAGE Package;
-} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
)
},
{
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT (
OFFSET_OF (RDN1EDGE_PPTT_PACKAGE , Cluster[0]),
PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0),
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [edk2-platforms][PATCH V4 4/9] Platform/Sgi: Update ACPI version to v6.4 for RD-N1-Edge-X2 platform
2022-06-27 6:04 [edk2-platforms][PATCH V4 0/9] Upadate the ACPI tables for RD platforms Pranav Madhu
` (2 preceding siblings ...)
2022-06-27 6:04 ` [edk2-platforms][PATCH V4 3/9] Platform/Sgi: Update ACPI version to v6.4 for RD-N1-Edge platform Pranav Madhu
@ 2022-06-27 6:04 ` Pranav Madhu
2022-06-27 6:04 ` [edk2-platforms][PATCH V4 5/9] Platform/Sgi: Update ACPI version to v6.4 for RD-E1-Edge platform Pranav Madhu
` (5 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Pranav Madhu @ 2022-06-27 6:04 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar, Pierre Gondois, Thomas Abraham
Update the RD-N1-Edge-X2 platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc | 52 ++++---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc | 151 ++++++++++----------
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc | 96 +++++++------
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Srat.aslc | 74 +++++-----
4 files changed, 200 insertions(+), 173 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
index 704708f94baf..4a55c33396b6 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
@@ -1,17 +1,25 @@
/** @file
-* Heterogeneous Memory Attribute Table (HMAT)
-*
-* Copyright (c) 2020-2021, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Heterogeneous Memory Attribute Table (HMAT)
+
+ The (HMAT) describes the memory attributes, such as memory side cache
+ attributes and bandwidth and latency details, related to Memory Proximity
+ Domains. The software is expected to use this information as a hint for
+ optimization, or when the system has heterogeneous memory. The attributes of
+ the memory connected to the two chips on this platform are listed in this
+ table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.27, Heterogeneous Memory Attribute Table
**/
-#include <IndustryStandard/Acpi.h>
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
-#include <SgiAcpiHeader.h>
-#include <SgiPlatform.h>
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CHIP_CNT FixedPcdGet32 (PcdChipCount)
#define INITATOR_PROXIMITY_DOMAIN_CNT 2
@@ -29,12 +37,12 @@ typedef struct InitiatorTargetProximityMatrix {
} INITIATOR_TARGET_PROXIMITY_MATRIX;
typedef struct {
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER Header;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES Proximity[CHIP_CNT];
- EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO LatencyInfo;
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER Header;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES Proximity[CHIP_CNT];
+ EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO LatencyInfo;
INITIATOR_TARGET_PROXIMITY_MATRIX Matrix;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache0;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache1;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache0;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache1;
} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE;
#pragma pack ()
@@ -43,9 +51,9 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
// Header
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE,
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
),
{
EFI_ACPI_RESERVED_BYTE,
@@ -57,15 +65,15 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
// Memory Proximity Domain
{
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x0, 0x0),
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x1, 0x1),
},
// Latency Info
- EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
- 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT, 100),
+ EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
+ 0, 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT, 100),
{
{0, 1},
{0, 1},
@@ -82,7 +90,7 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
},
// Memory Side Cache
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
0x0,
SIZE_8MB,
HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
@@ -94,7 +102,7 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
),
0),
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
0x1,
SIZE_8MB,
HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc
index f9210cc6226a..ecf444028e2e 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2019-2020, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-N1-Edge
+ dual chip platform is included in this table.
+
+ Copyright (c) 2019 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
-#include <IndustryStandard/Acpi.h>
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -23,114 +29,115 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_CNT * CHIP_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor[CHIP_CNT];
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CORE_CNT * CHIP_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor[CHIP_CNT];
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
- // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
+ // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
- // Efficiency)
+ // Efficiency,
+ // SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
- // (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
+ // (see note in 5.2.12.14 GICC Structure of ACPI v6.4).
// Chip - 0 CPUs
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-1
- 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-1
+ 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-2
- 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-2
+ 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-3
- 0, 3, GET_MPID(0x0, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-3
+ 0, 3, GET_MPID(0x0, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-4
- 0, 4, GET_MPID(0x100, 0x00), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-4
+ 0, 4, GET_MPID(0x100, 0x00), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-5
- 0, 5, GET_MPID(0x100, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-5
+ 0, 5, GET_MPID(0x100, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-6
- 0, 6, GET_MPID(0x100, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-6
+ 0, 6, GET_MPID(0x100, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-7
- 0, 7, GET_MPID(0x100, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-7
+ 0, 7, GET_MPID(0x100, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
// Chip - 1 CPUs
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-8
- 0, 8, GET_MPID(0x01000000ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-8
+ 0, 8, GET_MPID(0x01000000ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-9
- 0, 9, GET_MPID(0x01000000ULL, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-9
+ 0, 9, GET_MPID(0x01000000ULL, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-10
- 0, 10, GET_MPID(0x01000000ULL, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-10
+ 0, 10, GET_MPID(0x01000000ULL, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-11
- 0, 11, GET_MPID(0x01000000ULL, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-11
+ 0, 11, GET_MPID(0x01000000ULL, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-12
- 0, 12, GET_MPID(0x01000100ULL, 0x00ULL), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-12
+ 0, 12, GET_MPID(0x01000100ULL, 0x00ULL), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-13
- 0, 13, GET_MPID(0x01000100ULL, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-13
+ 0, 13, GET_MPID(0x01000100ULL, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-14
- 0, 14, GET_MPID(0x01000100ULL, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-14
+ 0, 14, GET_MPID(0x01000100ULL, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-15
- 0, 15, GET_MPID(0x01000100ULL, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-15
+ 0, 15, GET_MPID(0x01000100ULL, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */)
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0)
},
// GIC Distributor Entry
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
0, 3),
{
// GIC Redistributor for Chip 0
- EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
+ EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
SIZE_1MB),
// GIC Redistributor for Chip 1
- EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase)
+ EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase)
+ SGI_REMOTE_CHIP_MEM_OFFSET(1),
SIZE_1MB)
}
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc
index d78afb00c3b0..5b99fb27c72e 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc
@@ -1,30 +1,28 @@
/** @file
-* Processor Properties Topology Table (PPTT) for RD-N1-Edge dual-chip platform
-*
-* This file describes the topological structure of the processor block on the
-* RD-N1-Edge dual-chip platform in the form as defined by ACPI PPTT table. The
-* RD-N1-Edge dual-chip platform includes two RD-N1-Edge single-chip platforms
-* connected over cache coherent interconnect. Each of the RD-N1-Edge single-chip
-* platform includes two clusters with four single-thread CPUS. Each of the CPUs
-* include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache. Each
-* cluster includes a 2MB L3 cache. Each instance of the chip includes a system
-* level cache of 8MB.
-*
-* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-* @par Specification Reference:
-* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+ Processor Properties Topology Table (PPTT) for RD-N1-Edge dual-chip platform
+
+ This file describes the topological structure of the processor block on the
+ RD-N1-Edge dual-chip platform in the form as defined by ACPI PPTT table. The
+ RD-N1-Edge dual-chip platform includes two RD-N1-Edge single-chip platforms
+ connected over cache coherent interconnect. Each of the RD-N1-Edge single-chip
+ platform includes two clusters with four single-thread CPUS. Each of the CPUs
+ include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache. Each
+ cluster includes a 2MB L3 cache. Each instance of the chip includes a system
+ level cache of 8MB.
+
+ Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology Table
**/
-#include <IndustryStandard/Acpi.h>
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
-
-#include "SgiPlatform.h"
#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CHIP_COUNT FixedPcdGet32 (PcdChipCount)
@@ -37,10 +35,10 @@
#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) \
{ \
/* Parameters for CPU Core */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \
PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package[PackageId].Cluster[ClusterId]), /* Parent */ \
((PackageId << 3) | (ClusterId << 2) | CpuId), /* ACPI Id */ \
2 /* Num of private resource */ \
@@ -48,47 +46,53 @@
\
/* Offsets of the private resources */ \
{ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package[PackageId].Cluster[ClusterId].Core[CpuId].DCache), \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package[PackageId].Cluster[ClusterId].Core[CpuId].ICache) \
}, \
\
/* L1 data cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package[PackageId].Cluster[ClusterId].Core[CpuId].L2Cache), \
/* Next level of cache */ \
SIZE_64KB, /* Size */ \
256, /* Num of sets */ \
4, /* Associativity */ \
PPTT_DATA_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1DataCache) \
+ /* Cache id */ \
), \
\
/* L1 instruction cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package[PackageId].Cluster[ClusterId].Core[CpuId].L2Cache), \
/* Next level of cache */ \
SIZE_64KB, /* Size */ \
256, /* Num of sets */ \
4, /* Associativity */ \
PPTT_INST_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1InstructionCache) \
+ /* Cache id */ \
), \
\
/* L2 cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
0, /* Next level of cache */ \
SIZE_512KB, /* Size */ \
1024, /* Num of sets */ \
8, /* Associativity */ \
PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L2Cache) \
+ /* Cache id */ \
), \
}
@@ -100,28 +104,30 @@
#define PPTT_CLUSTER_INIT(PackageId, ClusterId) \
{ \
/* Parameters for Cluster */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
OFFSET_OF (RD_PPTT_CLUSTER, L3Cache), /* Length */ \
PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package[PackageId]), /* Parent */ \
((PackageId << 1) | ClusterId), /* ACPI Id */ \
1 /* Num of private resource */ \
), \
\
/* Offsets of the private resources */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package[PackageId].Cluster[ClusterId].L3Cache), \
\
/* L3 cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
0, /* Next level of cache */ \
SIZE_2MB, /* Size */ \
2048, /* Num of sets */ \
16, /* Associativity */ \
PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, 0, L3Cache) \
+ /* Cache id */ \
), \
\
/* Initialize child cores */ \
@@ -139,7 +145,7 @@
**/
#define PPTT_PACKAGE_INIT(PackageId) \
{ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
OFFSET_OF (RDN1EDGEX2_PPTT_PACKAGE , Cluster[0]), /* Length */ \
PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */ \
0, /* Parent */ \
@@ -155,7 +161,7 @@
#pragma pack(1)
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Package;
RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT];
} RDN1EDGEX2_PPTT_PACKAGE;
@@ -163,17 +169,17 @@ typedef struct {
* Processor Properties Topology Table
*/
typedef struct {
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
RDN1EDGEX2_PPTT_PACKAGE Package[CHIP_COUNT];
-} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
)
},
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Srat.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Srat.aslc
index 361db7506845..9be3f3f9b527 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Srat.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Srat.aslc
@@ -1,17 +1,23 @@
/** @file
-* Static Resource Affinity Table (SRAT)
-*
-* Copyright (c) 2020, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Static Resource Affinity Table (SRAT)
+
+ SRAT table provides information that allows OSPM to associate devices such as
+ processors with system locality / proximity domains and clock domains. The
+ memory attached to the two chips on this platform and its affinity to the
+ CPUs on its respective chips is listed in this table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.16, System Resource Affinity Table
**/
-#include "SgiAcpiHeader.h"
-#include "SgiPlatform.h"
-#include <IndustryStandard/Acpi.h>
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
//
// Static Resource Affinity Table
@@ -19,9 +25,9 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header;
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE Memory[4];
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE Gicc[16];
+ EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header;
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE Memory[4];
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE Gicc[16];
} EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE;
#pragma pack ()
@@ -30,9 +36,9 @@ EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat = {
// Header
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE,
EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE,
- EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION
+ EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION
),
0x00000001,
EFI_ACPI_RESERVED_QWORD
@@ -40,54 +46,54 @@ EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat = {
// Memory Affinity
{
// Chip 0 (2GB and 6GB)
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT (
0x0, FixedPcdGet64 (PcdSystemMemoryBase),
FixedPcdGet64 (PcdSystemMemorySize), 0x00000001),
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT (
0x0, FixedPcdGet64 (PcdDramBlock2Base),
FixedPcdGet64 (PcdDramBlock2Size), 0x00000001),
// Chip 1 (2GB and 6GB)
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT (
0x1, SYSTEM_MEMORY_BASE_REMOTE(1),
FixedPcdGet64 (PcdSystemMemorySize), 0x00000001),
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT (
0x1, DRAM_BLOCK2_BASE_REMOTE(1),
FixedPcdGet64 (PcdDramBlock2Size), 0x00000001),
},
// Processor Affinity
{
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x0, 0x00000000, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x0, 0x00000001, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x0, 0x00000002, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x0, 0x00000003, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x0, 0x00000004, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x0, 0x00000005, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x0, 0x00000006, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x0, 0x00000007, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x1, 0x00000008, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x1, 0x00000009, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x1, 0x0000000A, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x1, 0x0000000B, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x1, 0x0000000C, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x1, 0x0000000D, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x1, 0x0000000E, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x1, 0x0000000F, 0x00000001, 0x00000000),
},
};
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [edk2-platforms][PATCH V4 5/9] Platform/Sgi: Update ACPI version to v6.4 for RD-E1-Edge platform
2022-06-27 6:04 [edk2-platforms][PATCH V4 0/9] Upadate the ACPI tables for RD platforms Pranav Madhu
` (3 preceding siblings ...)
2022-06-27 6:04 ` [edk2-platforms][PATCH V4 4/9] Platform/Sgi: Update ACPI version to v6.4 for RD-N1-Edge-X2 platform Pranav Madhu
@ 2022-06-27 6:04 ` Pranav Madhu
2022-06-27 6:04 ` [edk2-platforms][PATCH V4 6/9] Platform/Sgi: Update ACPI version to v6.4 for RD-V1 platform Pranav Madhu
` (4 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Pranav Madhu @ 2022-06-27 6:04 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar, Pierre Gondois, Thomas Abraham
Update the RD-E1-Edge platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc | 247 ++++++++++----------
Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 109 ++++-----
2 files changed, 184 insertions(+), 172 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
index cb70394bfe91..0b2bba575bf5 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-E1-Edge
+ platform is included in this table.
+
+ Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
-#include <IndustryStandard/Acpi.h>
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -21,173 +27,174 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts;
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTURE GicIts;
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
- // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
+ // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
- // Efficiency)
+ // Efficiency,
+ // SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
// (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-0 Thread-0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-0 Thread-0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-1
- 0, 1, GET_MPID(0x0, 0x1), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-1
+ 0, 1, GET_MPID(0x0, 0x1), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-0
- 0, 2, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-0
+ 0, 2, GET_MPID(0x0, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-1
- 0, 3, GET_MPID(0x0, 0x101), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-1
+ 0, 3, GET_MPID(0x0, 0x101), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-2 Thread-0
- 0, 4, GET_MPID(0x0, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-2 Thread-0
+ 0, 4, GET_MPID(0x0, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-2 Thread-1
- 0, 5, GET_MPID(0x0, 0x201), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-2 Thread-1
+ 0, 5, GET_MPID(0x0, 0x201), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-3 Thread-0
- 0, 6, GET_MPID(0x0, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-3 Thread-0
+ 0, 6, GET_MPID(0x0, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-3 Thread-1
- 0, 7, GET_MPID(0x0, 0x301), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-3 Thread-1
+ 0, 7, GET_MPID(0x0, 0x301), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-4 Thread-0
- 0, 8, GET_MPID(0x0, 0x400), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-4 Thread-0
+ 0, 8, GET_MPID(0x0, 0x400), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-4 Thread-1
- 0, 9, GET_MPID(0x0, 0x401), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-4 Thread-1
+ 0, 9, GET_MPID(0x0, 0x401), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-5 Thread-0
- 0, 10, GET_MPID(0x0, 0x500), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-5 Thread-0
+ 0, 10, GET_MPID(0x0, 0x500), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-5 Thread-1
- 0, 11, GET_MPID(0x0, 0x501), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-5 Thread-1
+ 0, 11, GET_MPID(0x0, 0x501), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-6 Thread-0
- 0, 12, GET_MPID(0x0, 0x600), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-6 Thread-0
+ 0, 12, GET_MPID(0x0, 0x600), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-6 Thread-1
- 0, 13, GET_MPID(0x0, 0x601), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-6 Thread-1
+ 0, 13, GET_MPID(0x0, 0x601), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-7 Thread-0
- 0, 14, GET_MPID(0x0, 0x700), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-7 Thread-0
+ 0, 14, GET_MPID(0x0, 0x700), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-7 Thread-1
- 0, 15, GET_MPID(0x0, 0x701), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-7 Thread-1
+ 0, 15, GET_MPID(0x0, 0x701), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
//Cluster 1
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-0 Thread-0
- 0, 16, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-0 Thread-0
+ 0, 16, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-1
- 0, 17, GET_MPID(0x100, 0x1), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-1
+ 0, 17, GET_MPID(0x100, 0x1), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-0
- 0, 18, GET_MPID(0x100, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-0
+ 0, 18, GET_MPID(0x100, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-1
- 0, 19, GET_MPID(0x100, 0x101), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-1
+ 0, 19, GET_MPID(0x100, 0x101), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-2 Thread-0
- 0, 20, GET_MPID(0x100, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-2 Thread-0
+ 0, 20, GET_MPID(0x100, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-2 Thread-1
- 0, 21, GET_MPID(0x100, 0x201), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-2 Thread-1
+ 0, 21, GET_MPID(0x100, 0x201), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-3 Thread-0
- 0, 22, GET_MPID(0x100, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-3 Thread-0
+ 0, 22, GET_MPID(0x100, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-3 Thread-1
- 0, 23, GET_MPID(0x100, 0x301), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-3 Thread-1
+ 0, 23, GET_MPID(0x100, 0x301), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-4 Thread-0
- 0, 24, GET_MPID(0x100, 0x400), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-4 Thread-0
+ 0, 24, GET_MPID(0x100, 0x400), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-4 Thread-1
- 0, 25, GET_MPID(0x100, 0x401), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-4 Thread-1
+ 0, 25, GET_MPID(0x100, 0x401), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-5 Thread-0
- 0, 26, GET_MPID(0x100, 0x500), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-5 Thread-0
+ 0, 26, GET_MPID(0x100, 0x500), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-5 Thread-1
- 0, 27, GET_MPID(0x100, 0x501), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-5 Thread-1
+ 0, 27, GET_MPID(0x100, 0x501), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-6 Thread-0
- 0, 28, GET_MPID(0x100, 0x600), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-6 Thread-0
+ 0, 28, GET_MPID(0x100, 0x600), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-6 Thread-1
- 0, 29, GET_MPID(0x100, 0x601), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-6 Thread-1
+ 0, 29, GET_MPID(0x100, 0x601), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-7 Thread-0
- 0, 30, GET_MPID(0x100, 0x700), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-7 Thread-0
+ 0, 30, GET_MPID(0x100, 0x700), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-7 Thread-1
- 0, 31, GET_MPID(0x100, 0x701), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-7 Thread-1
+ 0, 31, GET_MPID(0x100, 0x701), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
},
// GIC Distributor Entry
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
0, 3),
// GIC Redistributor
- EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
+ EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
SIZE_8MB),
// GIC ITS
- EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000)
+ EFI_ACPI_6_4_GIC_ITS_INIT(0, 0x30040000)
};
//
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
index 0ef9607c0732..d5a06b344a52 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
@@ -1,28 +1,26 @@
/** @file
-* Processor Properties Topology Table (PPTT) for RD-E1-Edge platform
-*
-* This file describes the topological structure of the processor block on the
-* RD-E1-Edge platform in the form as defined by ACPI PPTT table. The RD-E1-Edge
-* platform includes two clusters with eight dual-thread CPUS. Each of the CPUs
-* include 32KB L1 Data cache, 32KB L1 Instruction cache and 256KB L2 cache.
-* Each cluster includes a 2MB L3 cache. The platform also includes a system
-* level cache of 8MB.
-*
-* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-* @par Specification Reference:
-* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+ Processor Properties Topology Table (PPTT) for RD-E1-Edge platform
+
+ This file describes the topological structure of the processor block on the
+ RD-E1-Edge platform in the form as defined by ACPI PPTT table. The RD-E1-Edge
+ platform includes two clusters with eight dual-thread CPUS. Each of the CPUs
+ include 32KB L1 Data cache, 32KB L1 Instruction cache and 256KB L2 cache.
+ Each cluster includes a 2MB L3 cache. The platform also includes a system
+ level cache of 8MB.
+
+ Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology Table
**/
-#include <IndustryStandard/Acpi.h>
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
-
-#include "SgiPlatform.h"
#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define THREAD_PER_CORE_E1 2
@@ -35,10 +33,10 @@
**/
#define PPTT_THREAD_INIT(PackageId, ClusterId, CpuId, ThreadId) \
{ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
sizeof (RDE1EDGE_PPTT_THREAD), /* Length */ \
PPTT_PROCESSOR_THREAD_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId]), /* Parent */ \
((PackageId << 5) | (ClusterId << 4) | (CpuId << 1) | ThreadId), \
/* ACPI Id */ \
@@ -55,10 +53,10 @@
#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) \
{ \
/* Parameters for CPU Core */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
OFFSET_OF (RDE1EDGE_PPTT_CORE, DCache), /* Length */ \
PPTT_PROCESSOR_CORE_THREADED_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId]), /* Parent */ \
0, /* ACPI Id */ \
2 /* Num of private resource */ \
@@ -66,47 +64,53 @@
\
/* Offsets of the private resources */ \
{ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].DCache), \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].ICache) \
}, \
\
/* L1 data cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
/* Next level of cache */ \
SIZE_32KB, /* Size */ \
128, /* Num of sets */ \
4, /* Associativity */ \
PPTT_DATA_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1DataCache) \
+ /* Cache id */ \
), \
\
/* L1 instruction cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
/* Next level of cache */ \
SIZE_32KB, /* Size */ \
128, /* Num of sets */ \
4, /* Associativity */ \
PPTT_INST_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1InstructionCache) \
+ /* Cache id */ \
), \
\
/* L2 cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
0, /* Next level of cache */ \
SIZE_256KB, /* Size */ \
1024, /* Num of sets */ \
4, /* Associativity */ \
PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L2Cache) \
+ /* Cache id */ \
), \
\
/* Thread Initialization */ \
@@ -124,28 +128,29 @@
#define PPTT_CLUSTER_INIT(PackageId, ClusterId) \
{ \
/* Parameters for Cluster */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
OFFSET_OF (RDE1EDGE_PPTT_CLUSTER, L3Cache), /* Length */ \
PPTT_PROCESSOR_CLUSTER_THREADED_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package), /* Parent */ \
0, /* ACPI Id */ \
1 /* Num of private resource */ \
), \
\
/* Offsets of the private resources */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].L3Cache), \
\
/* L3 cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
0, /* Next level of cache */ \
SIZE_2MB, /* Size */ \
2048, /* Num of sets */ \
16, /* Associativity */ \
PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, 0, L3Cache) /* Cache id */ \
), \
\
/* Initialize child cores */ \
@@ -167,7 +172,7 @@
**/
#define PPTT_PACKAGE_INIT(PackageId) \
{ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
OFFSET_OF (RDE1EDGE_PPTT_PACKAGE, Cluster[0]), \
PPTT_PROCESSOR_PACKAGE_FLAGS, \
0, \
@@ -182,27 +187,27 @@
#pragma pack(1)
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Thread;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Thread;
} RDE1EDGE_PPTT_THREAD;
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Core;
UINT32 Offset[2];
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE DCache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE ICache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE L2Cache;
RDE1EDGE_PPTT_THREAD Thread[THREAD_PER_CORE_E1];
} RDE1EDGE_PPTT_CORE;
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Cluster;
UINT32 Offset;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE L3Cache;
RDE1EDGE_PPTT_CORE Core[CORE_COUNT / THREAD_PER_CORE_E1];
} RDE1EDGE_PPTT_CLUSTER;
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Package;
RDE1EDGE_PPTT_CLUSTER Cluster[CLUSTER_COUNT];
} RDE1EDGE_PPTT_PACKAGE;
@@ -210,17 +215,17 @@ typedef struct {
* Processor Properties Topology Table
*/
typedef struct {
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
RDE1EDGE_PPTT_PACKAGE Package;
-} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
)
},
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [edk2-platforms][PATCH V4 6/9] Platform/Sgi: Update ACPI version to v6.4 for RD-V1 platform
2022-06-27 6:04 [edk2-platforms][PATCH V4 0/9] Upadate the ACPI tables for RD platforms Pranav Madhu
` (4 preceding siblings ...)
2022-06-27 6:04 ` [edk2-platforms][PATCH V4 5/9] Platform/Sgi: Update ACPI version to v6.4 for RD-E1-Edge platform Pranav Madhu
@ 2022-06-27 6:04 ` Pranav Madhu
2022-06-27 6:04 ` [edk2-platforms][PATCH V4 7/9] Platform/Sgi: Update ACPI version to v6.4 for RD-V1-MC platform Pranav Madhu
` (3 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Pranav Madhu @ 2022-06-27 6:04 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar, Pierre Gondois, Thomas Abraham
Update the RD-V1 platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc | 159 ++++++++++----------
Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 80 +++++-----
2 files changed, 125 insertions(+), 114 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc
index c4551e92c0f2..374b0e2bddbf 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2020, Arm Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-V1 platform
+ is included in this table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
-#include <IndustryStandard/Acpi.h>
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -21,110 +27,111 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts[4];
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTURE GicIts[4];
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
- // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
+ // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
- // Efficiency)
+ // Efficiency,
+ // SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
- // (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ // (see note in 5.2.12.14 GICC Structure of ACPI v6.4).
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1
- 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core1
+ 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2
- 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core2
+ 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core3
- 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core3
+ 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core4
- 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core4
+ 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core5
- 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core5
+ 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core6
- 0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core6
+ 0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core7
- 0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core7
+ 0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core8
- 0, 8, GET_MPID(0x800, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core8
+ 0, 8, GET_MPID(0x800, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core9
- 0, 9, GET_MPID(0x900, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core9
+ 0, 9, GET_MPID(0x900, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core10
- 0, 10, GET_MPID(0xa00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core10
+ 0, 10, GET_MPID(0xa00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core11
- 0, 11, GET_MPID(0xb00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core11
+ 0, 11, GET_MPID(0xb00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core12
- 0, 12, GET_MPID(0xc00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core12
+ 0, 12, GET_MPID(0xc00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core13
- 0, 13, GET_MPID(0xd00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core13
+ 0, 13, GET_MPID(0xd00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core14
- 0, 14, GET_MPID(0xe00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core14
+ 0, 14, GET_MPID(0xe00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core15
- 0, 15, GET_MPID(0xf00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core15
+ 0, 15, GET_MPID(0xf00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
},
// GIC Distributor Entry
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
0, 3),
// GIC Redistributor
- EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
+ EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
SIZE_16MB),
// GIC ITS
{
- EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000),
- EFI_ACPI_6_2_GIC_ITS_INIT(1, 0x30080000),
- EFI_ACPI_6_2_GIC_ITS_INIT(2, 0x300C0000),
- EFI_ACPI_6_2_GIC_ITS_INIT(3, 0x30100000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(0, 0x30040000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(1, 0x30080000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(2, 0x300C0000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(3, 0x30100000),
},
};
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc
index d8b73c804898..28416ae6b1c0 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc
@@ -1,27 +1,25 @@
/** @file
-* Processor Properties Topology Table (PPTT) for RD-V1 single-chip platform
-*
-* This file describes the topological structure of the processor block on the
-* RD-V1 single-chip platform in the form as defined by ACPI PPTT table. The
-* RD-V1 single-chip platform includes sixteen single-thread CPUS. Each of the
-* CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache.
-* The platform also includes a system level cache of 16MB.
-*
-* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-* @par Specification Reference:
-* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+ Processor Properties Topology Table (PPTT) for RD-V1 single-chip platform
+
+ This file describes the topological structure of the processor block on the
+ RD-V1 single-chip platform in the form as defined by ACPI PPTT table. The
+ RD-V1 single-chip platform includes sixteen single-thread CPUS. Each of the
+ CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache.
+ The platform also includes a system level cache of 16MB.
+
+ Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology Table
**/
-#include <IndustryStandard/Acpi.h>
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
-
-#include "SgiPlatform.h"
#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
/** Define helper macro for populating processor core information.
@@ -32,10 +30,10 @@
#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) \
{ \
/* Parameters for CPU Core */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \
PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId]), /* Parent */ \
((PackageId << 4) | ClusterId), /* ACPI Id */ \
2 /* Num of private resource */ \
@@ -43,47 +41,53 @@
\
/* Offsets of the private resources */ \
{ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].DCache), \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].ICache) \
}, \
\
/* L1 data cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
/* Next level of cache */ \
SIZE_64KB, /* Size */ \
256, /* Num of sets */ \
4, /* Associativity */ \
PPTT_DATA_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1DataCache) \
+ /* Cache id */ \
), \
\
/* L1 instruction cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
/* Next level of cache */ \
SIZE_64KB, /* Size */ \
256, /* Num of sets */ \
4, /* Associativity */ \
PPTT_INST_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1InstructionCache) \
+ /* Cache id */ \
), \
\
/* L2 cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
0, /* Next level of cache */ \
SIZE_1MB, /* Size */ \
2048, /* Num of sets */ \
8, /* Associativity */ \
PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L2Cache) \
+ /* Cache id */ \
), \
}
@@ -95,10 +99,10 @@
#define PPTT_CLUSTER_INIT(PackageId, ClusterId) \
{ \
/* Parameters for Cluster */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ \
PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package), /* Parent */ \
((PackageId << 4) | ClusterId), /* ACPI Id */ \
0 /* Num of private resource */ \
@@ -115,22 +119,22 @@
* Processor Properties Topology Table
*/
typedef struct {
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
RD_PPTT_PACKAGE Package;
-} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
)
},
{
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT (
OFFSET_OF (RD_PPTT_PACKAGE, Cluster[0]),
PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0),
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [edk2-platforms][PATCH V4 7/9] Platform/Sgi: Update ACPI version to v6.4 for RD-V1-MC platform
2022-06-27 6:04 [edk2-platforms][PATCH V4 0/9] Upadate the ACPI tables for RD platforms Pranav Madhu
` (5 preceding siblings ...)
2022-06-27 6:04 ` [edk2-platforms][PATCH V4 6/9] Platform/Sgi: Update ACPI version to v6.4 for RD-V1 platform Pranav Madhu
@ 2022-06-27 6:04 ` Pranav Madhu
2022-06-27 6:04 ` [edk2-platforms][PATCH V4 8/9] Platform/Sgi: Update ACPI version to v6.4 for RD-N2 platform Pranav Madhu
` (2 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Pranav Madhu @ 2022-06-27 6:04 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar, Pierre Gondois, Thomas Abraham
Update the RD-V1-MC platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc | 64 ++++----
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Madt.aslc | 165 ++++++++++----------
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc | 84 +++++-----
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Srat.aslc | 82 +++++-----
4 files changed, 210 insertions(+), 185 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
index c2dad0e137d5..b8485cd98ea4 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
@@ -1,17 +1,25 @@
/** @file
-* Heterogeneous Memory Attribute Table (HMAT)
-*
-* Copyright (c) 2020-2021, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Heterogeneous Memory Attribute Table (HMAT)
+
+ The (HMAT) describes the memory attributes, such as memory side cache
+ attributes and bandwidth and latency details, related to Memory Proximity
+ Domains. The software is expected to use this information as a hint for
+ optimization, or when the system has heterogeneous memory. The attributes of
+ the memory connected to the two chips on this platform are listed in this
+ table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.27, Heterogeneous Memory Attribute Table
**/
-#include <IndustryStandard/Acpi.h>
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
-#include <SgiAcpiHeader.h>
-#include <SgiPlatform.h>
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CHIP_CNT FixedPcdGet32 (PcdChipCount)
#define INITATOR_PROXIMITY_DOMAIN_CNT 4
@@ -29,14 +37,14 @@ typedef struct InitiatorTargetProximityMatrix {
} INITIATOR_TARGET_PROXIMITY_MATRIX;
typedef struct {
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER Header;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES Proximity[CHIP_CNT];
- EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO LatencyInfo;
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER Header;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES Proximity[CHIP_CNT];
+ EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO LatencyInfo;
INITIATOR_TARGET_PROXIMITY_MATRIX Matrix;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache0;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache1;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache2;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache3;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache0;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache1;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache2;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache3;
} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE;
#pragma pack ()
@@ -45,9 +53,9 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
// Header
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE,
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
),
{
EFI_ACPI_RESERVED_BYTE,
@@ -59,19 +67,19 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
// Memory Proximity Domain
{
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x0, 0x0),
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x1, 0x1),
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x2, 0x2),
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x3, 0x3),
},
// Latency Info
- EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
- 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT, 100),
+ EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
+ 0, 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT, 100),
{
{0, 1, 2, 3},
{0, 1, 2, 3},
@@ -90,7 +98,7 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
},
// Memory Side Cache
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
0x0,
SIZE_1GB,
HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
@@ -102,7 +110,7 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
),
0),
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
0x1,
SIZE_1GB,
HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
@@ -114,7 +122,7 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
),
0),
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
0x2,
SIZE_1GB,
HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
@@ -126,7 +134,7 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
),
0),
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
0x3,
SIZE_1GB,
HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Madt.aslc
index 9b3e4f2be370..67687d627670 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2020, Arm Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-V1
+ multichip platform is included in this table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
-#include <IndustryStandard/Acpi.h>
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -22,125 +28,126 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_CNT * CHIP_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor[CHIP_CNT];
- EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts[4];
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CORE_CNT * CHIP_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor[CHIP_CNT];
+ EFI_ACPI_6_4_GIC_ITS_STRUCTURE GicIts[4];
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
- // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
+ // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
- // Efficiency)
+ // Efficiency,
+ // SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
- // (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
+ // (see note in 5.2.12.14 GICC Structure of ACPI v6.4).
//Chip 0
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1
- 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core1
+ 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2
- 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core2
+ 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core3
- 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core3
+ 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
// Chip 1
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0
- 0, 4, GET_MPID(0x01000000ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core0
+ 0, 4, GET_MPID(0x01000000ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1
- 0, 5, GET_MPID(0x01000100ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core1
+ 0, 5, GET_MPID(0x01000100ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2
- 0, 6, GET_MPID(0x01000200ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core2
+ 0, 6, GET_MPID(0x01000200ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core3
- 0, 7, GET_MPID(0x01000300ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core3
+ 0, 7, GET_MPID(0x01000300ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
// Chip 2
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0
- 0, 8, GET_MPID(0x02000000ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core0
+ 0, 8, GET_MPID(0x02000000ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1
- 0, 9, GET_MPID(0x02000100ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core1
+ 0, 9, GET_MPID(0x02000100ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2
- 0, 10, GET_MPID(0x02000200ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core2
+ 0, 10, GET_MPID(0x02000200ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core3
- 0, 11, GET_MPID(0x02000300ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core3
+ 0, 11, GET_MPID(0x02000300ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
// Chip 3
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0
- 0, 12, GET_MPID(0x03000000ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core0
+ 0, 12, GET_MPID(0x03000000ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1
- 0, 13, GET_MPID(0x03000100ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core1
+ 0, 13, GET_MPID(0x03000100ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2
- 0, 14, GET_MPID(0x03000200ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core2
+ 0, 14, GET_MPID(0x03000200ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core3
- 0, 15, GET_MPID(0x03000300ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core3
+ 0, 15, GET_MPID(0x03000300ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
},
// GIC Distributor Entry
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
0, 3),
{
// GIC Redistributor
- EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase) +
+ EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase) +
SGI_REMOTE_CHIP_MEM_OFFSET(0), SIZE_16MB),
- EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase) +
+ EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase) +
SGI_REMOTE_CHIP_MEM_OFFSET(1), SIZE_16MB),
- EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase) +
+ EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase) +
SGI_REMOTE_CHIP_MEM_OFFSET(2), SIZE_16MB),
- EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase) +
+ EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase) +
SGI_REMOTE_CHIP_MEM_OFFSET(3), SIZE_16MB)
},
// GIC ITS
{
- EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000),
- EFI_ACPI_6_2_GIC_ITS_INIT(1, 0x30080000),
- EFI_ACPI_6_2_GIC_ITS_INIT(2, 0x300C0000),
- EFI_ACPI_6_2_GIC_ITS_INIT(3, 0x30100000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(0, 0x30040000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(1, 0x30080000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(2, 0x300C0000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(3, 0x30100000),
},
};
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc
index 82124ca2ab65..a99b683eb66c 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc
@@ -1,29 +1,27 @@
/** @file
-* Processor Properties Topology Table (PPTT) for RD-V1 quad-chip platform
-*
-* This file describes the topological structure of the processor block on the
-* RD-V1 quad-chip platform in the form as defined by ACPI PPTT table. The RD-V1
-* quad-chip platform is composed of four identical chips connected over cache
-* coherent interconnect. Each of the chip on the platform includes four single
-* thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction
-* cache and 1MB L2 cache. The platform also includes a system level cache of
-* 16MB per chip.
-*
-* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-* @par Specification Reference:
-* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+ Processor Properties Topology Table (PPTT) for RD-V1 quad-chip platform
+
+ This file describes the topological structure of the processor block on the
+ RD-V1 quad-chip platform in the form as defined by ACPI PPTT table. The RD-V1
+ quad-chip platform is composed of four identical chips connected over cache
+ coherent interconnect. Each of the chip on the platform includes four single
+ thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction
+ cache and 1MB L2 cache. The platform also includes a system level cache of
+ 16MB per chip.
+
+ Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology Table
**/
-#include <IndustryStandard/Acpi.h>
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
-
-#include "SgiPlatform.h"
#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CHIP_COUNT FixedPcdGet32 (PcdChipCount)
@@ -36,10 +34,10 @@
#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) \
{ \
/* Parameters for CPU Core */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \
PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package[PackageId].Cluster[ClusterId]), /* Parent */ \
((PackageId << 2) | ClusterId), /* ACPI Id */ \
2 /* Num of private resource */ \
@@ -47,47 +45,53 @@
\
/* Offsets of the private resources */ \
{ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package[PackageId].Cluster[ClusterId].Core[CpuId].DCache), \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package[PackageId].Cluster[ClusterId].Core[CpuId].ICache) \
}, \
\
/* L1 data cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package[PackageId].Cluster[ClusterId].Core[CpuId].L2Cache), \
/* Next level of cache */ \
SIZE_64KB, /* Size */ \
256, /* Num of sets */ \
4, /* Associativity */ \
PPTT_DATA_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1DataCache) \
+ /* Cache id */ \
), \
\
/* L1 instruction cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package[PackageId].Cluster[ClusterId].Core[CpuId].L2Cache), \
/* Next level of cache */ \
SIZE_64KB, /* Size */ \
256, /* Num of sets */ \
4, /* Associativity */ \
PPTT_INST_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1InstructionCache) \
+ /* Cache id */ \
), \
\
/* L2 cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
0, /* Next level of cache */ \
SIZE_1MB, /* Size */ \
2048, /* Num of sets */ \
8, /* Associativity */ \
PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L2Cache) \
+ /* Cache id */ \
), \
}
@@ -99,10 +103,10 @@
#define PPTT_CLUSTER_INIT(PackageId, ClusterId) \
{ \
/* Parameters for Cluster */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ \
PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package[PackageId]), /* Parent */ \
((PackageId << 2) | ClusterId), /* ACPI Id */ \
0 /* Num of private resource */ \
@@ -120,7 +124,7 @@
**/
#define PPTT_PACKAGE_INIT(PackageId) \
{ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
OFFSET_OF (RD_PPTT_PACKAGE, Cluster[0]), /* Length */ \
PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */ \
0, /* Parent */ \
@@ -140,17 +144,17 @@
* Processor Properties Topology Table
*/
typedef struct {
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
RD_PPTT_PACKAGE Package[CHIP_COUNT];
-} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
)
},
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Srat.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Srat.aslc
index 2ad72e3878c2..b12db67dfe3f 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Srat.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Srat.aslc
@@ -1,17 +1,23 @@
/** @file
-* Static Resource Affinity Table (SRAT)
-*
-* Copyright (c) 2020, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Static Resource Affinity Table (SRAT)
+
+ SRAT table provides information that allows OSPM to associate devices such as
+ processors with system locality / proximity domains and clock domains. The
+ memory attached to the two chips on this platform and its affinity to the
+ CPUs on its respective chips is listed in this table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.16, System Resource Affinity Table
**/
-#include "SgiAcpiHeader.h"
-#include "SgiPlatform.h"
-#include <IndustryStandard/Acpi.h>
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
//
// Static Resource Affinity Table
@@ -19,9 +25,9 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header;
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE Memory[8];
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE Gicc[16];
+ EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header;
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE Memory[8];
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE Gicc[16];
} EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE;
#pragma pack ()
@@ -30,9 +36,9 @@ EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat = {
// Header
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE,
EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE,
- EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION
+ EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION
),
0x00000001,
EFI_ACPI_RESERVED_QWORD
@@ -40,70 +46,70 @@ EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat = {
// Memory Affinity
{
// Chip 0 (2GB and 6GB)
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT (
0x0, FixedPcdGet64 (PcdSystemMemoryBase),
FixedPcdGet64 (PcdSystemMemorySize), 0x00000001),
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT (
0x0, FixedPcdGet64 (PcdDramBlock2Base),
FixedPcdGet64 (PcdDramBlock2Size), 0x00000001),
// Chip 1 (2GB and 6GB)
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT (
0x1, SYSTEM_MEMORY_BASE_REMOTE(1),
FixedPcdGet64 (PcdSystemMemorySize), 0x00000001),
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT (
0x1, DRAM_BLOCK2_BASE_REMOTE(1),
FixedPcdGet64 (PcdDramBlock2Size), 0x00000001),
// Chip 2 (2GB and 6GB)
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT (
0x2, SYSTEM_MEMORY_BASE_REMOTE(2),
FixedPcdGet64 (PcdSystemMemorySize), 0x00000001),
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT (
0x2, DRAM_BLOCK2_BASE_REMOTE(2),
FixedPcdGet64 (PcdDramBlock2Size), 0x00000001),
// Chip 3 (2GB and 6GB)
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT(
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT(
0x3, SYSTEM_MEMORY_BASE_REMOTE(3),
FixedPcdGet64 (PcdSystemMemorySize), 0x00000001),
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT(
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT(
0x3, DRAM_BLOCK2_BASE_REMOTE(3),
FixedPcdGet64 (PcdDramBlock2Size), 0x00000001),
},
// Processor Affinity
{
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x0, 0x00000000, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x0, 0x00000001, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x0, 0x00000002, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x0, 0x00000003, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x1, 0x00000004, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x1, 0x00000005, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x1, 0x00000006, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x1, 0x00000007, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x2, 0x00000008, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x2, 0x00000009, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x2, 0x0000000A, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x2, 0x0000000B, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x3, 0x0000000C, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x3, 0x0000000D, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x3, 0x0000000E, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x3, 0x0000000F, 0x00000001, 0x00000000),
},
};
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [edk2-platforms][PATCH V4 8/9] Platform/Sgi: Update ACPI version to v6.4 for RD-N2 platform
2022-06-27 6:04 [edk2-platforms][PATCH V4 0/9] Upadate the ACPI tables for RD platforms Pranav Madhu
` (6 preceding siblings ...)
2022-06-27 6:04 ` [edk2-platforms][PATCH V4 7/9] Platform/Sgi: Update ACPI version to v6.4 for RD-V1-MC platform Pranav Madhu
@ 2022-06-27 6:04 ` Pranav Madhu
2022-06-27 6:04 ` [edk2-platforms][PATCH V4 9/9] Platform/Sgi: Update ACPI version to v6.4 for RD-N2-Cfg1 platform Pranav Madhu
2022-06-28 7:19 ` [edk2-platforms][PATCH V4 0/9] Upadate the ACPI tables for RD platforms Ard Biesheuvel
9 siblings, 0 replies; 11+ messages in thread
From: Pranav Madhu @ 2022-06-27 6:04 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar, Pierre Gondois, Thomas Abraham
Update the RD-N2 platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc | 163 ++++++++++----------
Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 80 +++++-----
2 files changed, 127 insertions(+), 116 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc
index dbb23683113a..cdf8b3f2e953 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2020, Arm Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-N2 platform
+ is included in this table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
-#include <IndustryStandard/Acpi.h>
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -21,112 +27,113 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts[6];
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTURE GicIts[6];
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
- // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
+ // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
- // Efficiency)
+ // Efficiency,
+ // SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
- // (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ // (see note in 5.2.12.14 GICC Structure of ACPI v6.4).
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core1
- 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core1
+ 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core2
- 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core2
+ 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core3
- 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core3
+ 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core4
- 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core4
+ 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core5
- 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core5
+ 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core6
- 0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core6
+ 0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core7
- 0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core7
+ 0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core8
- 0, 8, GET_MPID(0x800, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core8
+ 0, 8, GET_MPID(0x800, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core9
- 0, 9, GET_MPID(0x900, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core9
+ 0, 9, GET_MPID(0x900, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core10
- 0, 10, GET_MPID(0xa00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core10
+ 0, 10, GET_MPID(0xa00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core11
- 0, 11, GET_MPID(0xb00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core11
+ 0, 11, GET_MPID(0xb00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core12
- 0, 12, GET_MPID(0xc00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core12
+ 0, 12, GET_MPID(0xc00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core13
- 0, 13, GET_MPID(0xd00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core13
+ 0, 13, GET_MPID(0xd00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core14
- 0, 14, GET_MPID(0xe00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core14
+ 0, 14, GET_MPID(0xe00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core15
- 0, 15, GET_MPID(0xf00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core15
+ 0, 15, GET_MPID(0xf00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
},
// GIC Distributor Entry
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
0, 3),
// GIC Redistributor
- EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
+ EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
SIZE_16MB),
// GIC ITS
{
- EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000),
- EFI_ACPI_6_2_GIC_ITS_INIT(1, 0x30080000),
- EFI_ACPI_6_2_GIC_ITS_INIT(2, 0x300C0000),
- EFI_ACPI_6_2_GIC_ITS_INIT(3, 0x30100000),
- EFI_ACPI_6_2_GIC_ITS_INIT(4, 0x30140000),
- EFI_ACPI_6_2_GIC_ITS_INIT(5, 0x30180000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(0, 0x30040000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(1, 0x30080000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(2, 0x300C0000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(3, 0x30100000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(4, 0x30140000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(5, 0x30180000),
},
};
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
index 2ee566145382..b8cb04459be2 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
@@ -1,27 +1,25 @@
/** @file
-* Processor Properties Topology Table (PPTT) for RD-N2 platform
-*
-* This file describes the topological structure of the processor block on the
-* RD-N2 platform in the form as defined by ACPI PPTT table. The RD-N2 platform
-* includes sixteen single-thread CPUS. Each of the CPUs include 64KB L1 Data
-* cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also includes
-* system level cache of 32MB.
-*
-* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-* @par Specification Reference:
-* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+ Processor Properties Topology Table (PPTT) for RD-N2 platform
+
+ This file describes the topological structure of the processor block on the
+ RD-N2 platform in the form as defined by ACPI PPTT table. The RD-N2 platform
+ includes sixteen single-thread CPUS. Each of the CPUs include 64KB L1 Data
+ cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also includes
+ system level cache of 32MB.
+
+ Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology Table
**/
-#include <IndustryStandard/Acpi.h>
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
-
-#include "SgiPlatform.h"
#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
/** Define helper macro for populating processor core information.
@@ -32,10 +30,10 @@
#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) \
{ \
/* Parameters for CPU Core */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \
PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId]), /* Parent */ \
((PackageId << 4) | ClusterId), /* ACPI Id */ \
2 /* Num of private resource */ \
@@ -43,47 +41,53 @@
\
/* Offsets of the private resources */ \
{ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].DCache), \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].ICache) \
}, \
\
/* L1 data cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
/* Next level of cache */ \
SIZE_64KB, /* Size */ \
256, /* Num of sets */ \
4, /* Associativity */ \
PPTT_DATA_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1DataCache) \
+ /* Cache id */ \
), \
\
/* L1 instruction cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
/* Next level of cache */ \
SIZE_64KB, /* Size */ \
256, /* Num of sets */ \
4, /* Associativity */ \
PPTT_INST_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1InstructionCache) \
+ /* Cache id */ \
), \
\
/* L2 cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
0, /* Next level of cache */ \
SIZE_1MB, /* Size */ \
2048, /* Num of sets */ \
8, /* Associativity */ \
PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L2Cache) \
+ /* Cache id */ \
), \
}
@@ -95,10 +99,10 @@
#define PPTT_CLUSTER_INIT(PackageId, ClusterId) \
{ \
/* Parameters for Cluster */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ \
PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package), /* Parent */ \
((PackageId << 4) | ClusterId), /* ACPI Id */ \
0 /* Num of private resource */ \
@@ -115,22 +119,22 @@
* Processor Properties Topology Table
*/
typedef struct {
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
RD_PPTT_PACKAGE Package;
-} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
)
},
{
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT (
OFFSET_OF (RD_PPTT_PACKAGE, Cluster[0]),
PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0),
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [edk2-platforms][PATCH V4 9/9] Platform/Sgi: Update ACPI version to v6.4 for RD-N2-Cfg1 platform
2022-06-27 6:04 [edk2-platforms][PATCH V4 0/9] Upadate the ACPI tables for RD platforms Pranav Madhu
` (7 preceding siblings ...)
2022-06-27 6:04 ` [edk2-platforms][PATCH V4 8/9] Platform/Sgi: Update ACPI version to v6.4 for RD-N2 platform Pranav Madhu
@ 2022-06-27 6:04 ` Pranav Madhu
2022-06-28 7:19 ` [edk2-platforms][PATCH V4 0/9] Upadate the ACPI tables for RD platforms Ard Biesheuvel
9 siblings, 0 replies; 11+ messages in thread
From: Pranav Madhu @ 2022-06-27 6:04 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar, Pierre Gondois, Thomas Abraham
Update the RD-N2-Cfg1 platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc | 112 ++++++++++----------
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc | 76 ++++++-------
2 files changed, 96 insertions(+), 92 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
index c6bb29a25c61..65926027eadf 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
@@ -1,23 +1,22 @@
/** @file
-* Multiple APIC Description Table (MADT) for RD-N2-Cfg1 platform
-*
-* This file lists all the processors available on the platform that the OSPM
-* can enumerate and boot. It also lists all the interrupt controllers available
-* in the system.
-*
-* Copyright (c) 2021, Arm Ltd. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-* @par Specification Reference:
-* - ACPI 6.3, Chapter 5, Section 5.2.12, Multiple APIC Description Table
+ Multiple APIC Description Table (MADT) for RD-N2-Cfg1 platform
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-N2-Cfg1
+ platform is included in this table.
+
+ Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
-#include <IndustryStandard/Acpi.h>
-
#include "SgiAcpiHeader.h"
#include "SgiPlatform.h"
@@ -28,69 +27,70 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts[3];
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTURE GicIts[3];
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
- // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
+ // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
- // Efficiency)
+ // Efficiency,
+ // SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
- // (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core1
- 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core2
- 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core3
- 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core4
- 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core5
- 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core6
- 0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core7
- 0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
+ // (see chapter 5.2.12.14 GICC Structure of ACPI v6.4).
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core1
+ 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core2
+ 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core3
+ 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core4
+ 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core5
+ 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core6
+ 0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core7
+ 0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
},
// GIC Distributor Entry
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
0, 3),
// GIC Redistributor
- EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
+ EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
SIZE_16MB),
// GIC ITS
{
- EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000),
- EFI_ACPI_6_2_GIC_ITS_INIT(1, 0x30080000),
- EFI_ACPI_6_2_GIC_ITS_INIT(2, 0x300C0000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(0, 0x30040000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(1, 0x30080000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(2, 0x300C0000),
},
};
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc
index 54eb6d6c41b3..454ed58ea8e6 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc
@@ -1,24 +1,22 @@
/** @file
-* Processor Properties Topology Table (PPTT) for RD-N2-Cfg1 platform
-*
-* This file describes the topological structure of the processor block on the
-* RD-N2-Cfg1 platform in the form as defined by ACPI PPTT table. The RD-N2-Cfg1
-* platform includes eight single-thread CPUS. Each of the CPUs include 64KB
-* L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also
-* includes system level cache of 8MB.
-*
-* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-* @par Specification Reference:
-* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+ Processor Properties Topology Table (PPTT) for RD-N2-Cfg1 platform
+
+ This file describes the topological structure of the processor block on the
+ RD-N2-Cfg1 platform in the form as defined by ACPI PPTT table. The RD-N2-Cfg1
+ platform includes eight single-thread CPUS. Each of the CPUs include 64KB
+ L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also
+ includes system level cache of 8MB.
+
+ Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology Table
**/
-#include <IndustryStandard/Acpi.h>
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
-
#include "SgiAcpiHeader.h"
#include "SgiPlatform.h"
@@ -31,10 +29,10 @@
#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) \
{ \
/* Parameters for CPU Core */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \
PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId]), /* Parent */ \
((PackageId << 4) | ClusterId), /* ACPI Id */ \
2 /* Num of private resource */ \
@@ -42,47 +40,53 @@
\
/* Offsets of the private resources */ \
{ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].DCache), \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].ICache) \
}, \
\
/* L1 data cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
/* Next level of cache */ \
SIZE_64KB, /* Size */ \
256, /* Num of sets */ \
4, /* Associativity */ \
PPTT_DATA_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1DataCache) \
+ /* Cache id */ \
), \
\
/* L1 instruction cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
/* Next level of cache */ \
SIZE_64KB, /* Size */ \
256, /* Num of sets */ \
4, /* Associativity */ \
PPTT_INST_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1InstructionCache) \
+ /* Cache id */ \
), \
\
/* L2 cache parameters */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
0, /* Next level of cache */ \
SIZE_1MB, /* Size */ \
2048, /* Num of sets */ \
8, /* Associativity */ \
PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
- 64 /* Line size */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L2Cache) \
+ /* Cache id */ \
), \
}
@@ -94,10 +98,10 @@
#define PPTT_CLUSTER_INIT(PackageId, ClusterId) \
{ \
/* Parameters for Cluster */ \
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ \
PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
Package), /* Parent */ \
((PackageId << 4) | ClusterId), /* ACPI Id */ \
0 /* Num of private resource */ \
@@ -114,22 +118,22 @@
* Processor Properties Topology Table
*/
typedef struct {
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
RD_PPTT_PACKAGE Package;
-} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
)
},
{
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT (
OFFSET_OF (RD_PPTT_PACKAGE, Cluster[0]),
PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0),
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [edk2-platforms][PATCH V4 0/9] Upadate the ACPI tables for RD platforms
2022-06-27 6:04 [edk2-platforms][PATCH V4 0/9] Upadate the ACPI tables for RD platforms Pranav Madhu
` (8 preceding siblings ...)
2022-06-27 6:04 ` [edk2-platforms][PATCH V4 9/9] Platform/Sgi: Update ACPI version to v6.4 for RD-N2-Cfg1 platform Pranav Madhu
@ 2022-06-28 7:19 ` Ard Biesheuvel
9 siblings, 0 replies; 11+ messages in thread
From: Ard Biesheuvel @ 2022-06-28 7:19 UTC (permalink / raw)
To: Pranav Madhu
Cc: edk2-devel-groups-io, Ard Biesheuvel, Sami Mujawar,
Pierre Gondois, Thomas Abraham
On Mon, 27 Jun 2022 at 08:05, Pranav Madhu <pranav.madhu@arm.com> wrote:
>
> Changes since V3:
> - Addressed comments from Pierre Gondois
> - Rebased on top of latest master branch
>
> Changes since V2:
> - Rebased on top of latest master branch
> - Update PPTT table with unique cache ID across the system for different
> levels of cache.
>
> Changes since V1:
> - Rebased on top of latest master branch.
> - Rebased on top of patch to remove SLC cache entries from PPTT (link
> for the same in edk2.groups.io is provided below)
>
> Arm infrastructure reference design platforms uses ACPI tables to
> provide the hardware information to the operating system. Currently the
> ACPI tables are aligned with ACPI v6.2 and v6.3 specification. This
> patch series update the tables to ACPI v6.4 specificaion. Features like
> MPAM relies on cache ID field of PPTT tables to distinguish between
> different physical caches, which is introduced in PPTT table in ACPI
> v6.4. Also ServerReady (SBBR compliaance) strictly recomments all the
> tables in the system should allign with same version of ACPI. Hence
> upgrade all ACPI tables mentioned in ACPI specification to v6.4.
>
>
> The first patch in this series update the generic tables which are
> common for all platfoms. The subsequent patches in this series update
> platform specific ACPI tables to v6.4 for the respective platform.
>
> This patch series also update the headers in the .aslc files to match
> the coding style as per edk2 coding guidelines.
>
> Link to github branch with the patches in this series -
> https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/acpi64_for_rd_platforms
>
> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
> Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
>
> Pranav Madhu (9):
> Platform/Sgi: Update ACPI version to v6.4
> Platform/Sgi: Update ACPI version to v6.4 for SGI575 platform
> Platform/Sgi: Update ACPI version to v6.4 for RD-N1-Edge platform
> Platform/Sgi: Update ACPI version to v6.4 for RD-N1-Edge-X2 platform
> Platform/Sgi: Update ACPI version to v6.4 for RD-E1-Edge platform
> Platform/Sgi: Update ACPI version to v6.4 for RD-V1 platform
> Platform/Sgi: Update ACPI version to v6.4 for RD-V1-MC platform
> Platform/Sgi: Update ACPI version to v6.4 for RD-N2 platform
> Platform/Sgi: Update ACPI version to v6.4 for RD-N2-Cfg1 platform
>
Merged as 433b5b1b0f7f..750f6807879b
Thanks all,
^ permalink raw reply [flat|nested] 11+ messages in thread