From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web09.38430.1656309919348667246 for ; Sun, 26 Jun 2022 23:05:19 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: pranav.madhu@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4C9E3175A; Sun, 26 Jun 2022 23:05:19 -0700 (PDT) Received: from usa.arm.com (unknown [10.162.16.33]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6E9FF3F5A1; Sun, 26 Jun 2022 23:05:17 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Sami Mujawar , Pierre Gondois , Thomas Abraham Subject: [edk2-platforms][PATCH V4 5/9] Platform/Sgi: Update ACPI version to v6.4 for RD-E1-Edge platform Date: Mon, 27 Jun 2022 11:34:45 +0530 Message-Id: <20220627060449.522959-6-pranav.madhu@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220627060449.522959-1-pranav.madhu@arm.com> References: <20220627060449.522959-1-pranav.madhu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Update the RD-E1-Edge platform specific ACPI tables to ACPI version v6.4. Significant changes introduced are to add SPE overflow interrupt number field to GICC structure of MADT table and adding cache ID field to the cache structure of PPTT table. Signed-off-by: Pranav Madhu Reviewed-by: Pierre Gondois Reviewed-by: Thomas Abraham --- Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc | 247 ++++++++++------= ---- Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 109 ++++----- 2 files changed, 184 insertions(+), 172 deletions(-) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc b/Platform= /ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc index cb70394bfe91..0b2bba575bf5 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc @@ -1,18 +1,24 @@ /** @file -* Multiple APIC Description Table (MADT) -* -* Copyright (c) 2018-2020, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* + Multiple APIC Description Table (MADT) + + The MADT table provides OSPM with information necessary for operation = on + systems with Generic interrupt controller (GIC). The information about= the GIC + CPU interface, redistributor, distributor and ITS blocks on the Rd-E1-= Edge + platform is included in this table. + + Copyright (c) 2018 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Tab= le **/ =20 -#include "SgiPlatform.h" -#include "SgiAcpiHeader.h" #include #include #include -#include +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" =20 #define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \ FixedPcdGet32 (PcdCoreCount)) @@ -21,173 +27,174 @@ #pragma pack (1) =20 typedef struct { - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; - EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CO= RE_CNT]; - EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; - EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor= ; - EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts; -} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE; + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CO= RE_CNT]; + EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor= ; + EFI_ACPI_6_4_GIC_ITS_STRUCTURE GicIts; +} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE; =20 #pragma pack () =20 -STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { +STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { { ARM_ACPI_HEADER ( - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE, - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION ), // MADT specific fields 0, // LocalApicAddress 0 // Flags }, { - // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr= , Flags, + // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr= , Flags, // PmuIrq, GicBase, GicVBas= e, // GicHBase, GsivId, GicRBa= se, - // Efficiency) + // Efficiency, + // SpeOverflowInterrupt) // Note: The GIC Structure of the primary CPU must be the first entr= y // (see note in 5.2.12.14 GICC Structure of ACPI v6.2). - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-0 Thread-0 - 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-0 Thread-0 + 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-1 - 0, 1, GET_MPID(0x0, 0x1), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-1 + 0, 1, GET_MPID(0x0, 0x1), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-0 - 0, 2, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-0 + 0, 2, GET_MPID(0x0, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-1 - 0, 3, GET_MPID(0x0, 0x101), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-1 + 0, 3, GET_MPID(0x0, 0x101), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-2 Thread-0 - 0, 4, GET_MPID(0x0, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-2 Thread-0 + 0, 4, GET_MPID(0x0, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-2 Thread-1 - 0, 5, GET_MPID(0x0, 0x201), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-2 Thread-1 + 0, 5, GET_MPID(0x0, 0x201), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-3 Thread-0 - 0, 6, GET_MPID(0x0, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-3 Thread-0 + 0, 6, GET_MPID(0x0, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-3 Thread-1 - 0, 7, GET_MPID(0x0, 0x301), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-3 Thread-1 + 0, 7, GET_MPID(0x0, 0x301), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), =20 - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-4 Thread-0 - 0, 8, GET_MPID(0x0, 0x400), EFI_ACPI_6_2_GIC_ENABLED, 23, + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-4 Thread-0 + 0, 8, GET_MPID(0x0, 0x400), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-4 Thread-1 - 0, 9, GET_MPID(0x0, 0x401), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-4 Thread-1 + 0, 9, GET_MPID(0x0, 0x401), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-5 Thread-0 - 0, 10, GET_MPID(0x0, 0x500), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-5 Thread-0 + 0, 10, GET_MPID(0x0, 0x500), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-5 Thread-1 - 0, 11, GET_MPID(0x0, 0x501), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-5 Thread-1 + 0, 11, GET_MPID(0x0, 0x501), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-6 Thread-0 - 0, 12, GET_MPID(0x0, 0x600), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-6 Thread-0 + 0, 12, GET_MPID(0x0, 0x600), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-6 Thread-1 - 0, 13, GET_MPID(0x0, 0x601), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-6 Thread-1 + 0, 13, GET_MPID(0x0, 0x601), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-7 Thread-0 - 0, 14, GET_MPID(0x0, 0x700), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-7 Thread-0 + 0, 14, GET_MPID(0x0, 0x700), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-7 Thread-1 - 0, 15, GET_MPID(0x0, 0x701), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-7 Thread-1 + 0, 15, GET_MPID(0x0, 0x701), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), =20 //Cluster 1 - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-0 Thread-0 - 0, 16, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-0 Thread-0 + 0, 16, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-1 - 0, 17, GET_MPID(0x100, 0x1), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-1 + 0, 17, GET_MPID(0x100, 0x1), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-0 - 0, 18, GET_MPID(0x100, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-0 + 0, 18, GET_MPID(0x100, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-1 - 0, 19, GET_MPID(0x100, 0x101), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-1 + 0, 19, GET_MPID(0x100, 0x101), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-2 Thread-0 - 0, 20, GET_MPID(0x100, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-2 Thread-0 + 0, 20, GET_MPID(0x100, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-2 Thread-1 - 0, 21, GET_MPID(0x100, 0x201), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-2 Thread-1 + 0, 21, GET_MPID(0x100, 0x201), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-3 Thread-0 - 0, 22, GET_MPID(0x100, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-3 Thread-0 + 0, 22, GET_MPID(0x100, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-3 Thread-1 - 0, 23, GET_MPID(0x100, 0x301), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-3 Thread-1 + 0, 23, GET_MPID(0x100, 0x301), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-4 Thread-0 - 0, 24, GET_MPID(0x100, 0x400), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-4 Thread-0 + 0, 24, GET_MPID(0x100, 0x400), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-4 Thread-1 - 0, 25, GET_MPID(0x100, 0x401), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-4 Thread-1 + 0, 25, GET_MPID(0x100, 0x401), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-5 Thread-0 - 0, 26, GET_MPID(0x100, 0x500), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-5 Thread-0 + 0, 26, GET_MPID(0x100, 0x500), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-5 Thread-1 - 0, 27, GET_MPID(0x100, 0x501), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-5 Thread-1 + 0, 27, GET_MPID(0x100, 0x501), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-6 Thread-0 - 0, 28, GET_MPID(0x100, 0x600), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-6 Thread-0 + 0, 28, GET_MPID(0x100, 0x600), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-6 Thread-1 - 0, 29, GET_MPID(0x100, 0x601), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-6 Thread-1 + 0, 29, GET_MPID(0x100, 0x601), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-7 Thread-0 - 0, 30, GET_MPID(0x100, 0x700), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-7 Thread-0 + 0, 30, GET_MPID(0x100, 0x700), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-7 Thread-1 - 0, 31, GET_MPID(0x100, 0x701), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-7 Thread-1 + 0, 31, GET_MPID(0x100, 0x701), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), }, // GIC Distributor Entry - EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorB= ase), + EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorB= ase), 0, 3), // GIC Redistributor - EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributor= sBase), + EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributor= sBase), SIZE_8MB), // GIC ITS - EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000) + EFI_ACPI_6_4_GIC_ITS_INIT(0, 0x30040000) }; =20 // diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc b/Platform= /ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc index 0ef9607c0732..d5a06b344a52 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc @@ -1,28 +1,26 @@ /** @file -* Processor Properties Topology Table (PPTT) for RD-E1-Edge platform -* -* This file describes the topological structure of the processor block o= n the -* RD-E1-Edge platform in the form as defined by ACPI PPTT table. The RD-= E1-Edge -* platform includes two clusters with eight dual-thread CPUS. Each of th= e CPUs -* include 32KB L1 Data cache, 32KB L1 Instruction cache and 256KB L2 cac= he. -* Each cluster includes a 2MB L3 cache. The platform also includes a sys= tem -* level cache of 8MB. -* -* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* @par Specification Reference: -* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology= Table + Processor Properties Topology Table (PPTT) for RD-E1-Edge platform + + This file describes the topological structure of the processor block o= n the + RD-E1-Edge platform in the form as defined by ACPI PPTT table. The RD-= E1-Edge + platform includes two clusters with eight dual-thread CPUS. Each of th= e CPUs + include 32KB L1 Data cache, 32KB L1 Instruction cache and 256KB L2 cac= he. + Each cluster includes a 2MB L3 cache. The platform also includes a sys= tem + level cache of 8MB. + + Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology= Table **/ =20 -#include #include #include #include - -#include "SgiPlatform.h" #include "SgiAcpiHeader.h" +#include "SgiPlatform.h" =20 #define THREAD_PER_CORE_E1 2 =20 @@ -35,10 +33,10 @@ **/ #define PPTT_THREAD_INIT(PackageId, ClusterId, CpuId, ThreadId) = \ { = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ sizeof (RDE1EDGE_PPTT_THREAD), /* Length */ = \ PPTT_PROCESSOR_THREAD_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId]), /* Parent */ = \ ((PackageId << 5) | (ClusterId << 4) | (CpuId << 1) | ThreadId), = \ /* ACPI Id */ = \ @@ -55,10 +53,10 @@ #define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) = \ { = \ /* Parameters for CPU Core */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ OFFSET_OF (RDE1EDGE_PPTT_CORE, DCache), /* Length */ = \ PPTT_PROCESSOR_CORE_THREADED_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId]), /* Parent */ = \ 0, /* ACPI Id */ = \ 2 /* Num of private resour= ce */ \ @@ -66,47 +64,53 @@ = \ /* Offsets of the private resources */ = \ { = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].DCache), = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].ICache) = \ }, = \ = \ /* L1 data cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].L2Cache), = \ /* Next level of cache */ = \ SIZE_32KB, /* Size */ = \ 128, /* Num of sets */ = \ 4, /* Associativity */ = \ PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1DataCache) = \ + /* Cache id */ = \ ), = \ = \ /* L1 instruction cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].L2Cache), = \ /* Next level of cache */ = \ SIZE_32KB, /* Size */ = \ 128, /* Num of sets */ = \ 4, /* Associativity */ = \ PPTT_INST_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1InstructionCache) = \ + /* Cache id */ = \ ), = \ = \ /* L2 cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ 0, /* Next level of cache */ = \ SIZE_256KB, /* Size */ = \ 1024, /* Num of sets */ = \ 4, /* Associativity */ = \ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L2Cache) = \ + /* Cache id */ = \ ), = \ = \ /* Thread Initialization */ = \ @@ -124,28 +128,29 @@ #define PPTT_CLUSTER_INIT(PackageId, ClusterId) = \ { = \ /* Parameters for Cluster */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ OFFSET_OF (RDE1EDGE_PPTT_CLUSTER, L3Cache), /* Length */ = \ PPTT_PROCESSOR_CLUSTER_THREADED_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package), /* Parent */ = \ 0, /* ACPI Id */ = \ 1 /* Num of private resource *= / \ ), = \ = \ /* Offsets of the private resources */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].L3Cache), = \ = \ /* L3 cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ 0, /* Next level of cache */ = \ SIZE_2MB, /* Size */ = \ 2048, /* Num of sets */ = \ 16, /* Associativity */ = \ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + RD_PPTT_CACHE_ID(PackageId, ClusterId, 0, L3Cache) /* Cache id = */ \ ), = \ = \ /* Initialize child cores */ = \ @@ -167,7 +172,7 @@ **/ #define PPTT_PACKAGE_INIT(PackageId) = \ { = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ OFFSET_OF (RDE1EDGE_PPTT_PACKAGE, Cluster[0]), = \ PPTT_PROCESSOR_PACKAGE_FLAGS, = \ 0, = \ @@ -182,27 +187,27 @@ =20 #pragma pack(1) typedef struct { - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Thread; + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Thread; } RDE1EDGE_PPTT_THREAD; =20 typedef struct { - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core; + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Core; UINT32 Offset[2]; - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache; - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache; - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache; + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE DCache; + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE ICache; + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE L2Cache; RDE1EDGE_PPTT_THREAD Thread[THREAD_PER_CORE_E1]; } RDE1EDGE_PPTT_CORE; =20 typedef struct { - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster; + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Cluster; UINT32 Offset; - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache; + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE L3Cache; RDE1EDGE_PPTT_CORE Core[CORE_COUNT / THREAD_PER_CO= RE_E1]; } RDE1EDGE_PPTT_CLUSTER; =20 typedef struct { - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Package; RDE1EDGE_PPTT_CLUSTER Cluster[CLUSTER_COUNT]; } RDE1EDGE_PPTT_PACKAGE; =20 @@ -210,17 +215,17 @@ typedef struct { * Processor Properties Topology Table */ typedef struct { - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; RDE1EDGE_PPTT_PACKAGE Package; -} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; #pragma pack () =20 -STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { +STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { { ARM_ACPI_HEADER ( - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATU= RE, - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATU= RE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION ) }, =20 --=20 2.25.1