* [edk2-platforms][PATCH V1 3/5] Platform/Sgi: Add ACPI tables for RD-N2-Cfg2 platform
2022-06-27 6:40 [edk2-platforms][PATCH V1 0/5] Platform/Sgi: Add initial support for RD-N2-Cfg2 platform Pranav Madhu
2022-06-27 6:40 ` [edk2-platforms][PATCH V1 1/5] Platform/Sgi: Add a new PCD for defining addressable bits per chip Pranav Madhu
2022-06-27 6:40 ` [edk2-platforms][PATCH V1 2/5] Platform/Sgi: Add ProductId lookup values for RD-N2-Cfg2 Platform Pranav Madhu
@ 2022-06-27 6:40 ` Pranav Madhu
2022-06-27 6:40 ` [edk2-platforms][PATCH V1 4/5] Platform/Sgi: Add support for RD-N2-Cfg2 Platform Pranav Madhu
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Pranav Madhu @ 2022-06-27 6:40 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar
From: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Add MADT, DSDT and SRAT ACPI tables that are specific for RD-N2-Cfg2
platform. The rest of the ACPI tables are reused from the shared ACPI
tables in SgiPkg.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2AcpiTables.inf | 71 +++
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Dsdt.asl | 532 ++++++++++++++++++++
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Madt.aslc | 145 ++++++
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Pptt.aslc | 172 +++++++
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Srat.aslc | 117 +++++
5 files changed, 1037 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2AcpiTables.inf
new file mode 100644
index 000000000000..2354f2dc65eb
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2AcpiTables.inf
@@ -0,0 +1,71 @@
+## @file
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2022, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = RdN2Cfg2AcpiTables
+ FILE_GUID = c712719a-0aaf-438c-9cdd-35ab4d60207d # gArmSgiAcpiTablesGuid
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Dbg2.aslc
+ Fadt.aslc
+ Gtdt.aslc
+ RdN2Cfg2/Dsdt.asl
+ RdN2Cfg2/Madt.aslc
+ RdN2Cfg2/Pptt.aslc
+ RdN2Cfg2/Srat.aslc
+ Spcr.aslc
+ SsdtRos.asl
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/ARM/SgiPkg/SgiPlatform.dec
+
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+ gArmPlatformTokenSpaceGuid.PcdClusterCount
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgInterrupt
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
+ gArmPlatformTokenSpaceGuid.PL011UartInterrupt
+
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+
+ gArmSgiTokenSpaceGuid.PcdChipCount
+ gArmSgiTokenSpaceGuid.PcdDramBlock2Base
+ gArmSgiTokenSpaceGuid.PcdDramBlock2Size
+ gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
+ gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
+ gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip
+ gArmSgiTokenSpaceGuid.PcdOscLpiEnable
+ gArmSgiTokenSpaceGuid.PcdOscCppcEnable
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkSize
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt
+ gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress
+ gArmSgiTokenSpaceGuid.PcdVirtioNetSize
+ gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt
+ gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv
+ gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Dsdt.asl
new file mode 100644
index 000000000000..94d65fbbda2c
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Dsdt.asl
@@ -0,0 +1,532 @@
+/** @file
+ Differentiated System Description Table (DSDT) for RD-N2-Cfg2 platform
+
+ This file describes the peripheral devices, system hardware features and the
+ information about supported power events.
+
+ Copyright (c) 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.11.1, Differentiated System Description
+ Table (DSDT)
+**/
+
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
+
+DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
+ EFI_ACPI_ARM_OEM_REVISION) {
+
+ Scope (_SB) {
+
+ /* _OSC: Operating System Capabilities */
+ Method (_OSC, 4, Serialized) {
+ CreateDWordField (Arg3, 0x00, STS0)
+ CreateDWordField (Arg3, 0x04, CAP0)
+
+ /* Platform-wide Capabilities */
+ If (LEqual (Arg0, ToUUID("0811b06e-4a27-44f9-8d60-3cbbc22e7b48"))) {
+ /* OSC rev 1 supported, for other version, return failure */
+ If (LEqual (Arg1, One)) {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+
+ If (And (CAP0, OSC_CAP_OS_INITIATED_LPI)) {
+ /* OS initiated LPI not supported */
+ And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
+ Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+ }
+
+ If (And (CAP0, OSC_CAP_PLAT_COORDINATED_LPI)) {
+ if (LEqual (FixedPcdGet32 (PcdOscLpiEnable), Zero)) {
+ And (CAP0, Not (OSC_CAP_PLAT_COORDINATED_LPI), CAP0)
+ Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+ }
+ }
+
+ If (And (CAP0, OSC_CAP_CPPC_SUPPORT)) {
+ /* CPPC revision 1 and below not supported */
+ And (CAP0, Not (OSC_CAP_CPPC_SUPPORT), CAP0)
+ Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+ }
+
+ If (And (CAP0, OSC_CAP_CPPC2_SUPPORT)) {
+ if (LEqual (FixedPcdGet32 (PcdOscCppcEnable), Zero)) {
+ And (CAP0, Not (OSC_CAP_CPPC2_SUPPORT), CAP0)
+ Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+ }
+ }
+ } Else {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+ Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
+ }
+ } Else {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+ Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_UUID), STS0)
+ }
+
+ Return (Arg3)
+ }
+
+ Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */
+ 0, // Version
+ 0, // Level Index
+ 2, // Count
+ Package () { // WFI for CPU
+ 1, // Min residency (uS)
+ 1, // Wake latency (uS)
+ 1, // Flags
+ 0, // Arch Context lost Flags (no loss)
+ 0, // Residency Counter Frequency
+ 0, // No parent state
+ ResourceTemplate () { // Register Entry method
+ Register (FFixedHW,
+ 32, // Bit Width
+ 0, // Bit Offset
+ 0xFFFFFFFF, // Address
+ 3, // Access Size
+ )
+ },
+ ResourceTemplate () { // Null Residency Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ ResourceTemplate () { // Null Usage Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ "LPI1-Core"
+ },
+ Package () { // Power Gating state for CPU
+ 150, // Min residency (uS)
+ 350, // Wake latency (uS)
+ 1, // Flags
+ 1, // Arch Context lost Flags (Core context lost)
+ 0, // Residency Counter Frequency
+ 0, // No parent state
+ ResourceTemplate () { // Register Entry method
+ Register (FFixedHW,
+ 32, // Bit Width
+ 0, // Bit Offset
+ 0x40000002, // Address (PwrLvl:core, StateTyp:PwrDn)
+ 3, // Access Size
+ ) },
+ ResourceTemplate () { // Null Residency Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ ResourceTemplate () { // Null Usage Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ "LPI3-Core"
+ },
+ })
+
+ Device (CL00) { // Cluster 0
+ Name (_HID, "ACPI0010")
+ Name (_UID, 0)
+
+ Device (CP00) { // Neoverse N2 core 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0)
+ Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000500, 0x06000504, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (0)
+ })
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
+
+ }
+ }
+
+ Device (CL01) { // Cluster 1
+ Name (_HID, "ACPI0010")
+ Name (_UID, 1)
+
+ Device (CP01) { // Neoverse N2 core 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 1)
+ Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000518, 0x0600051C, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (1)
+ })
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
+
+ }
+ }
+
+ Device (CL02) { // Cluster 2
+ Name (_HID, "ACPI0010")
+ Name (_UID, 2)
+
+ Device (CP02) { // Neoverse N2 core 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 2)
+ Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000530, 0x06000534, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (2)
+ })
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
+
+ }
+ }
+
+ Device (CL03) { // Cluster 3
+ Name (_HID, "ACPI0010")
+ Name (_UID, 3)
+
+ Device (CP03) { // Neoverse N2 core 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 3)
+ Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000548, 0x0600054C, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (3)
+ })
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
+
+ }
+ }
+
+ Device (CL04) { // Cluster 4
+ Name (_HID, "ACPI0010")
+ Name (_UID, 4)
+
+ Device (CP04) { // Neoverse N2 core 4
+ Name (_HID, "ACPI0007")
+ Name (_UID, 4)
+ Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x400006000500, 0x400006000504, 20, 160, 160, 115,
+ 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (4)
+ })
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
+
+ }
+ }
+
+ Device (CL05) { // Cluster 5
+ Name (_HID, "ACPI0010")
+ Name (_UID, 5)
+
+ Device (CP05) { // Neoverse N2 core 5
+ Name (_HID, "ACPI0007")
+ Name (_UID, 5)
+ Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x400006000518, 0x40000600051C, 20, 160, 160, 115,
+ 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (5)
+ })
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
+
+ }
+ }
+
+ Device (CL06) { // Cluster 6
+ Name (_HID, "ACPI0010")
+ Name (_UID, 6)
+
+ Device (CP06) { // Neoverse N2 core 6
+ Name (_HID, "ACPI0007")
+ Name (_UID, 6)
+ Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x400006000530, 0x400006000534, 20, 160, 160, 115,
+ 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (6)
+ })
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
+
+ }
+ }
+
+ Device (CL07) { // Cluster 7
+ Name (_HID, "ACPI0010")
+ Name (_UID, 7)
+
+ Device (CP07) { // Neoverse N2 core 7
+ Name (_HID, "ACPI0007")
+ Name (_UID, 7)
+ Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x400006000548, 0x40000600054C, 20, 160, 160, 115,
+ 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (7)
+ })
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
+
+ }
+ }
+
+ Device (CL08) { // Cluster 8
+ Name (_HID, "ACPI0010")
+ Name (_UID, 8)
+
+ Device (CP08) { // Neoverse N2 core 8
+ Name (_HID, "ACPI0007")
+ Name (_UID, 8)
+ Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x800006000500, 0x800006000504, 20, 160, 160, 115,
+ 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (8)
+ })
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
+
+ }
+ }
+
+ Device (CL09) { // Cluster 9
+ Name (_HID, "ACPI0010")
+ Name (_UID, 9)
+
+ Device (CP09) { // Neoverse N2 core 9
+ Name (_HID, "ACPI0007")
+ Name (_UID, 9)
+ Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x800006000518, 0x80000600051C, 20, 160, 160, 115,
+ 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (9)
+ })
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
+
+ }
+ }
+
+ Device (CL10) { // Cluster 10
+ Name (_HID, "ACPI0010")
+ Name (_UID, 10)
+
+ Device (CP10) { // Neoverse N2 core 10
+ Name (_HID, "ACPI0007")
+ Name (_UID, 10)
+ Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x800006000530, 0x800006000534, 20, 160, 160, 115,
+ 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (10)
+ })
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
+
+ }
+ }
+
+ Device (CL11) { // Cluster 11
+ Name (_HID, "ACPI0010")
+ Name (_UID, 11)
+
+ Device (CP11) { // Neoverse N2 core 11
+ Name (_HID, "ACPI0007")
+ Name (_UID, 11)
+ Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x800006000548, 0x80000600054C, 20, 160, 160, 115,
+ 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (11)
+ })
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
+
+ }
+ }
+
+ Device (CL12) { // Cluster 12
+ Name (_HID, "ACPI0010")
+ Name (_UID, 12)
+
+ Device (CP12) { // Neoverse N2 core 12
+ Name (_HID, "ACPI0007")
+ Name (_UID, 12)
+ Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0xC00006000500, 0xC00006000504, 20, 160, 160, 115,
+ 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (12)
+ })
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
+ }
+ }
+
+ Device (CL13) { // Cluster 13
+ Name (_HID, "ACPI0010")
+ Name (_UID, 13)
+
+ Device (CP13) { // Neoverse N2 core 13
+ Name (_HID, "ACPI0007")
+ Name (_UID, 13)
+ Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0xC00006000518, 0xC0000600051C, 20, 160, 160, 115,
+ 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (13)
+ })
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
+ }
+ }
+
+ Device (CL14) { // Cluster 14
+ Name (_HID, "ACPI0010")
+ Name (_UID, 14)
+
+ Device (CP14) { // Neoverse N2 core 14
+ Name (_HID, "ACPI0007")
+ Name (_UID, 14)
+ Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0xC00006000530, 0xC00006000534, 20, 160, 160, 115,
+ 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (14)
+ })
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
+ }
+ }
+
+ Device (CL15) { // Cluster 15
+ Name (_HID, "ACPI0010")
+ Name (_UID, 15)
+
+ Device (CP15) { // Neoverse N2 core 15
+ Name (_HID, "ACPI0007")
+ Name (_UID, 15)
+ Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0xC00006000548, 0xC0000600054C, 20, 160, 160, 115,
+ 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (15)
+ })
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
+ }
+ }
+
+ } // Scope(_SB)
+}
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Madt.aslc
new file mode 100644
index 000000000000..044d8d9b690b
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Madt.aslc
@@ -0,0 +1,145 @@
+/** @file
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the GIC
+ CPU interface, redistributor, distributor and ITS blocks on the RD-N2-Cfg2
+ platform is included in this table.
+
+ Copyright (c) 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
+**/
+
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
+
+#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
+ FixedPcdGet32 (PcdCoreCount))
+#define CHIP_CNT (FixedPcdGet32 (PcdChipCount))
+
+// Multiple APIC Description Table
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CORE_CNT * CHIP_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor[CHIP_CNT];
+ EFI_ACPI_6_4_GIC_ITS_STRUCTURE GicIts[6];
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ ),
+ // MADT specific fields
+ 0, // LocalApicAddress
+ 0 // Flags
+ },
+ {
+ // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
+ // PmuIrq, GicBase, GicVBase,
+ // GicHBase, GsivId, GicRBase,
+ // Efficiency,
+ // SpeOverflowInterrupt)
+ // Note: The GIC Structure of the primary CPU must be the first entry
+ // (see chapter 5.2.12.14 GICC Structure of ACPI v6.4).
+
+ // Chip 0
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core1
+ 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core2
+ 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core3
+ 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+
+ // Chip 1
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core0
+ 0, 4, GET_MPID(0x01000000ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core1
+ 0, 5, GET_MPID(0x01000100ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core2
+ 0, 6, GET_MPID(0x01000200ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core3
+ 0, 7, GET_MPID(0x01000300ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+
+ // Chip 2
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core0
+ 0, 8, GET_MPID(0x02000000ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core1
+ 0, 9, GET_MPID(0x02000100ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core2
+ 0, 10, GET_MPID(0x02000200ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core3
+ 0, 11, GET_MPID(0x02000300ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+
+ // Chip 3
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core0
+ 0, 12, GET_MPID(0x03000000ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core1
+ 0, 13, GET_MPID(0x03000100ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core2
+ 0, 14, GET_MPID(0x03000200ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core3
+ 0, 15, GET_MPID(0x03000300ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+ },
+ // GIC Distributor Entry
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
+ 0, 3),
+ {
+ // GIC Redistributor
+ EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase) +
+ SGI_REMOTE_CHIP_MEM_OFFSET(0), SIZE_16MB),
+ EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase) +
+ SGI_REMOTE_CHIP_MEM_OFFSET(1), SIZE_16MB),
+ EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase) +
+ SGI_REMOTE_CHIP_MEM_OFFSET(2), SIZE_16MB),
+ EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase) +
+ SGI_REMOTE_CHIP_MEM_OFFSET(3), SIZE_16MB)
+ },
+ // GIC ITS
+ {
+ EFI_ACPI_6_4_GIC_ITS_INIT(0, 0x30040000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(1, 0x30080000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(2, 0x300C0000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(3, 0x30100000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(4, 0x30140000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(5, 0x30180000),
+ },
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing
+// the data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Madt;
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Pptt.aslc
new file mode 100644
index 000000000000..3f37243a9d8a
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Pptt.aslc
@@ -0,0 +1,172 @@
+/** @file
+ Processor Properties Topology Table (PPTT) for RD-N2-Cfg2 platform
+
+ This file describes the topological structure of the processor block on the
+ RD-N2-Cfg2 platform in the form as defined by ACPI PPTT table. The RD-N2-Cfg2
+ platform is composed of four identical chips connected over cache coherent
+ interconnect. Each of the chip on the platform includes four single thread
+ CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache
+ and 1MB L2 cache.
+
+ Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
+
+#define CHIP_COUNT FixedPcdGet32 (PcdChipCount)
+
+/** Define helper macro for populating processor core information.
+
+ @param [in] PackageId Package instance number.
+ @param [in] ClusterId Cluster instance number.
+ @param [in] CpuId CPU instance number.
+**/
+#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) \
+ { \
+ /* Parameters for CPU Core */ \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[PackageId].Cluster[ClusterId]), /* Parent */ \
+ ((PackageId << 2) | ClusterId), /* ACPI Id */ \
+ 2 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ { \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[PackageId].Cluster[ClusterId].Core[CpuId].DCache), \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[PackageId].Cluster[ClusterId].Core[CpuId].ICache) \
+ }, \
+ \
+ /* L1 data cache parameters */ \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[PackageId].Cluster[ClusterId].Core[CpuId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1DataCache) \
+ /* Cache id */ \
+ ), \
+ \
+ /* L1 instruction cache parameters */ \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[PackageId].Cluster[ClusterId].Core[CpuId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_INST_CACHE_ATTR, /* Attributes */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1InstructionCache) \
+ /* Cache id */ \
+ ), \
+ \
+ /* L2 cache parameters */ \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_1MB, /* Size */ \
+ 2048, /* Num of sets */ \
+ 8, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64, /* Line size */ \
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L2Cache) \
+ /* Cache id */ \
+ ), \
+ }
+
+/** Define helper macro for populating processor container information.
+
+ @param [in] PackageId Package instance number.
+ @param [in] ClusterId Cluster instance number.
+**/
+#define PPTT_CLUSTER_INIT(PackageId, ClusterId) \
+ { \
+ /* Parameters for Cluster */ \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ \
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[PackageId]), /* Parent */ \
+ ((PackageId << 2) | ClusterId), /* ACPI Id */ \
+ 0 /* Num of private resource */ \
+ ), \
+ \
+ /* Initialize child core */ \
+ { \
+ PPTT_CORE_INIT (PackageId, ClusterId, 0) \
+ } \
+ }
+
+/** Define helper macro for populating SoC package information.
+
+ @param [in] PackageId Package instance number.
+**/
+#define PPTT_PACKAGE_INIT(PackageId) \
+ { \
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_PACKAGE, Cluster[0]), /* Length */ \
+ PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */ \
+ 0, /* Parent */ \
+ 0, /* ACPI Id */ \
+ 0 /* Num of private resource */ \
+ ), \
+ { \
+ PPTT_CLUSTER_INIT (PackageId, 0), \
+ PPTT_CLUSTER_INIT (PackageId, 1), \
+ PPTT_CLUSTER_INIT (PackageId, 2), \
+ PPTT_CLUSTER_INIT (PackageId, 3), \
+ } \
+ }
+
+#pragma pack(1)
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RD_PPTT_PACKAGE Package[CHIP_COUNT];
+} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ PPTT_PACKAGE_INIT (0),
+ PPTT_PACKAGE_INIT (1),
+ PPTT_PACKAGE_INIT (2),
+ PPTT_PACKAGE_INIT (3)
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from removing
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable = &Pptt;
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Srat.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Srat.aslc
new file mode 100644
index 000000000000..6bdad7004fb6
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Srat.aslc
@@ -0,0 +1,117 @@
+/** @file
+ Static Resource Affinity Table (SRAT)
+
+ SRAT table provides information that allows OSPM to associate devices such as
+ processors with system locality / proximity domains and clock domains. The
+ memory attached to the two chips on this platform and its affinity to the
+ chips on its respective chips is listed in this table.
+
+ Copyright (c) 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.16, System Resource Affinity Table
+**/
+
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
+
+//
+// Static Resource Affinity Table
+//
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header;
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE Memory[8];
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE Gicc[16];
+} EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE;
+
+#pragma pack ()
+
+EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat = {
+ // Header
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE,
+ EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE,
+ EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION
+ ),
+ 0x00000001,
+ EFI_ACPI_RESERVED_QWORD
+ },
+ // Memory Affinity
+ {
+ // Chip 0 (2GB and 6GB)
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT (
+ 0x0, FixedPcdGet64 (PcdSystemMemoryBase),
+ FixedPcdGet64 (PcdSystemMemorySize), 0x00000001),
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT (
+ 0x0, FixedPcdGet64 (PcdDramBlock2Base),
+ FixedPcdGet64 (PcdDramBlock2Size), 0x00000001),
+
+ // Chip 1 (2GB and 6GB)
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT (
+ 0x1, SYSTEM_MEMORY_BASE_REMOTE(1),
+ FixedPcdGet64 (PcdSystemMemorySize), 0x00000001),
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT (
+ 0x1, DRAM_BLOCK2_BASE_REMOTE(1),
+ FixedPcdGet64 (PcdDramBlock2Size), 0x00000001),
+
+ // Chip 2 (2GB and 6GB)
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT (
+ 0x2, SYSTEM_MEMORY_BASE_REMOTE(2),
+ FixedPcdGet64 (PcdSystemMemorySize), 0x00000001),
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT (
+ 0x2, DRAM_BLOCK2_BASE_REMOTE(2),
+ FixedPcdGet64 (PcdDramBlock2Size), 0x00000001),
+
+ // Chip 3 (2GB and 6GB)
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT(
+ 0x3, SYSTEM_MEMORY_BASE_REMOTE(3),
+ FixedPcdGet64 (PcdSystemMemorySize), 0x00000001),
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT(
+ 0x3, DRAM_BLOCK2_BASE_REMOTE(3),
+ FixedPcdGet64 (PcdDramBlock2Size), 0x00000001),
+ },
+ // Processor Affinity
+ {
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x0, 0x00000000, 0x00000001, 0x00000000),
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x0, 0x00000001, 0x00000001, 0x00000000),
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x0, 0x00000002, 0x00000001, 0x00000000),
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x0, 0x00000003, 0x00000001, 0x00000000),
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x1, 0x00000004, 0x00000001, 0x00000000),
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x1, 0x00000005, 0x00000001, 0x00000000),
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x1, 0x00000006, 0x00000001, 0x00000000),
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x1, 0x00000007, 0x00000001, 0x00000000),
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x2, 0x00000008, 0x00000001, 0x00000000),
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x2, 0x00000009, 0x00000001, 0x00000000),
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x2, 0x0000000A, 0x00000001, 0x00000000),
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x2, 0x0000000B, 0x00000001, 0x00000000),
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x3, 0x0000000C, 0x00000001, 0x00000000),
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x3, 0x0000000D, 0x00000001, 0x00000000),
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x3, 0x0000000E, 0x00000001, 0x00000000),
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x3, 0x0000000F, 0x00000001, 0x00000000),
+ },
+};
+
+VOID* CONST ReferenceAcpiTable = &Srat;
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread