From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web10.38794.1656313696151732675 for ; Mon, 27 Jun 2022 00:08:16 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=XZTYITRK; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: w.sheng@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1656313696; x=1687849696; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=MXGjZ9uyqZxahdsDKViTIrJJtyFsSX4dWdzPdspThDU=; b=XZTYITRK7qaz7uhT8qc8ydeonEb9TYVTZxGTTYvgaoqPfkVX4YFXQqkG 827C5uTELHQzo/8jEKoWjiRkN9WOXlWFD6kN88JWoj3r5PLV4KDdfbVG1 Ct2u1oel6ThLjJs70LtuE22RqLKjRn3wiegBNwwpsiducRC/TMNmwUACU 4EDVqBNF8er3IL4ogkHtcTe+IBwdzIG/OVcZ1MnznpC1Y1HaMW+bavxKw /ulVZrSw5IT22blSLVQYczsl9FaY7S9Z3a412ut8Ht/rZnCt2KKDTK8HY br5T7UvCdzJkaTqTf3DVT8v4+TIxU8fT4gA7WuEqEv1fDhMPT7JMUKPw9 Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10390"; a="261792947" X-IronPort-AV: E=Sophos;i="5.92,225,1650956400"; d="scan'208";a="261792947" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2022 00:08:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,225,1650956400"; d="scan'208";a="692489774" Received: from shwdesssddpdwei.ccr.corp.intel.com ([10.239.157.43]) by fmsmga002.fm.intel.com with ESMTP; 27 Jun 2022 00:08:14 -0700 From: "Sheng Wei" To: devel@edk2.groups.io Cc: Jenny Huang , Ray Ni , Rangasai V Chaganty Subject: [PATCH] IntelSiliconPkg/VTd: Fix VTd Queued Invalidation IOTLB descriptor Date: Mon, 27 Jun 2022 15:08:11 +0800 Message-Id: <20220627070811.722-1-w.sheng@intel.com> X-Mailer: git-send-email 2.26.2.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable VTd Queued Invalidation IOTLB descriptor need to use CAP_REG.DWD and CAP_REG.DRD. Queued Invalidation descriptor is a 128 bits value. Register-based invalidation interface supported by hardware implementations of this architecture with Major Version 5 or lower (VER_REG). REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3964 Signed-off-by: Sheng Wei Cc: Jenny Huang Cc: Ray Ni Cc: Rangasai V Chaganty --- .../VTd/IntelVTdDmarPei/IntelVTdDmar.c | 32 +++++++++---------- .../VTd/IntelVTdDmarPei/IntelVTdDmarPei.h | 2 +- .../Feature/VTd/IntelVTdDxe/VtdReg.c | 2 +- 3 files changed, 17 insertions(+), 19 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Inte= lVTdDmar.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Inte= lVTdDmar.c index 0d372f6c..b5b78f77 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDma= r.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDma= r.c @@ -79,7 +79,7 @@ PerpareCacheInvalidationInterface ( IN VTD_UNIT_INFO *VTdUnitInfo=0D )=0D {=0D - UINT16 QiDescLength;=0D + UINT16 QueueSize;=0D UINT64 Reg64;=0D UINT32 Reg32;=0D VTD_ECAP_REG ECapReg;=0D @@ -122,18 +122,18 @@ PerpareCacheInvalidationInterface ( // Setup the IQ address, size and descriptor width through the Invalidat= ion Queue Address Register=0D //=0D if (VTdUnitInfo->QiDesc =3D=3D NULL) {=0D - VTdUnitInfo->QueueSize =3D 0;=0D - QiDescLength =3D 1 << (VTdUnitInfo->QueueSize + 8);=0D - VTdUnitInfo->QiDesc =3D (QI_DESC *) AllocatePages (EFI_SIZE_TO_PAGES(s= izeof(QI_DESC) * QiDescLength));=0D + QueueSize =3D 0;=0D + VTdUnitInfo->QiDescLength =3D 1 << (QueueSize + 8);=0D + VTdUnitInfo->QiDesc =3D (QI_DESC *) AllocatePages (EFI_SIZE_TO_PAGES (= sizeof (QI_DESC) * VTdUnitInfo->QiDescLength));=0D if (VTdUnitInfo->QiDesc =3D=3D NULL) {=0D DEBUG ((DEBUG_ERROR,"Could not Alloc Invalidation Queue Buffer.\n"))= ;=0D return EFI_OUT_OF_RESOURCES;=0D }=0D }=0D =0D - DEBUG ((DEBUG_INFO, "Invalidation Queue Length : %d\n", QiDescLength));= =0D + DEBUG ((DEBUG_INFO, "Invalidation Queue Length : %d\n", VTdUnitInfo->QiD= escLength));=0D Reg64 =3D (UINT64) (UINTN) VTdUnitInfo->QiDesc;=0D - Reg64 |=3D VTdUnitInfo->QueueSize;=0D + Reg64 |=3D QueueSize;=0D MmioWrite64 (VtdUnitBaseAddress + R_IQA_REG, Reg64);=0D =0D //=0D @@ -164,7 +164,6 @@ DisableQueuedInvalidationInterface ( )=0D {=0D UINT32 Reg32;=0D - UINT16 QiDescLength;=0D =0D if (VTdUnitInfo->EnableQueuedInvalidation !=3D 0) {=0D Reg32 =3D MmioRead32 (VTdUnitInfo->VtdUnitBaseAddress + R_GSTS_REG);=0D @@ -176,10 +175,9 @@ DisableQueuedInvalidationInterface ( } while ((Reg32 & B_GSTS_REG_QIES) !=3D 0);=0D =0D if (VTdUnitInfo->QiDesc !=3D NULL) {=0D - QiDescLength =3D 1 << (VTdUnitInfo->QueueSize + 8);=0D - FreePages(VTdUnitInfo->QiDesc, EFI_SIZE_TO_PAGES(sizeof(QI_DESC) * Q= iDescLength));=0D + FreePages(VTdUnitInfo->QiDesc, EFI_SIZE_TO_PAGES (sizeof (QI_DESC) *= VTdUnitInfo->QiDescLength));=0D VTdUnitInfo->QiDesc =3D NULL;=0D - VTdUnitInfo->QueueSize =3D 0;=0D + VTdUnitInfo->QiDescLength =3D 0;=0D }=0D =0D VTdUnitInfo->EnableQueuedInvalidation =3D 0;=0D @@ -239,10 +237,10 @@ SubmitQueuedInvalidationDescriptor ( return EFI_INVALID_PARAMETER;=0D }=0D =0D - QiDescLength =3D 1 << (VTdUnitInfo->QueueSize + 8);=0D + QiDescLength =3D VTdUnitInfo->QiDescLength;=0D BaseDesc =3D VTdUnitInfo->QiDesc;=0D =0D - DEBUG((DEBUG_INFO, "[0x%x] Submit QI Descriptor [0x%08x, 0x%08x]\n", VTd= UnitInfo->VtdUnitBaseAddress, Desc->Low, Desc->High));=0D + DEBUG((DEBUG_INFO, "[0x%x] Submit QI Descriptor [0x%016lx, 0x%016lx]\n",= VTdUnitInfo->VtdUnitBaseAddress, Desc->Low, Desc->High));=0D =0D BaseDesc[VTdUnitInfo->QiFreeHead].Low =3D Desc->Low;=0D BaseDesc[VTdUnitInfo->QiFreeHead].High =3D Desc->High;=0D @@ -251,7 +249,6 @@ SubmitQueuedInvalidationDescriptor ( DEBUG((DEBUG_INFO,"QI Free Head=3D0x%x\n", VTdUnitInfo->QiFreeHead));=0D VTdUnitInfo->QiFreeHead =3D (VTdUnitInfo->QiFreeHead + 1) % QiDescLength= ;=0D =0D - Reg64Iqh =3D MmioRead64 (VTdUnitInfo->VtdUnitBaseAddress + R_IQH_REG);=0D //=0D // Update the HW tail register indicating the presence of new descriptor= s.=0D //=0D @@ -328,6 +325,7 @@ InvalidateIOTLB ( {=0D UINT64 Reg64;=0D VTD_ECAP_REG ECapReg;=0D + VTD_CAP_REG CapReg;=0D QI_DESC QiDesc;=0D =0D if (VTdUnitInfo->EnableQueuedInvalidation =3D=3D 0) {=0D @@ -353,8 +351,8 @@ InvalidateIOTLB ( //=0D // Queued Invalidation=0D //=0D - ECapReg.Uint64 =3D MmioRead64 (VTdUnitInfo->VtdUnitBaseAddress + R_ECA= P_REG);=0D - QiDesc.Low =3D QI_IOTLB_DID(0) | QI_IOTLB_DR(CAP_READ_DRAIN(ECapReg.Ui= nt64)) | QI_IOTLB_DW(CAP_WRITE_DRAIN(ECapReg.Uint64)) | QI_IOTLB_GRAN(1) | = QI_IOTLB_TYPE;=0D + CapReg.Uint64 =3D MmioRead64 (VTdUnitInfo->VtdUnitBaseAddress + R_CAP_= REG);=0D + QiDesc.Low =3D QI_IOTLB_DID(0) | QI_IOTLB_DR(CAP_READ_DRAIN(CapReg.Uin= t64)) | QI_IOTLB_DW(CAP_WRITE_DRAIN(CapReg.Uint64)) | QI_IOTLB_GRAN(1) | QI= _IOTLB_TYPE;=0D QiDesc.High =3D QI_IOTLB_ADDR(0) | QI_IOTLB_IH(0) | QI_IOTLB_AM(0);=0D =0D return SubmitQueuedInvalidationDescriptor(VTdUnitInfo, &QiDesc);=0D @@ -364,7 +362,7 @@ InvalidateIOTLB ( }=0D =0D /**=0D - Enable DMAR translation inpre-mem phase.=0D + Enable DMAR translation in pre-mem phase.=0D =0D @param[in] VtdUnitBaseAddress The base address of the VTd engine.=0D @param[in] RtaddrRegValue The value of RTADDR_REG.=0D @@ -400,7 +398,7 @@ EnableDmarPreMem ( Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_FEDATA_REG);=0D =0D //=0D - // Write Buffer Flush before invalidation=0D + // Write Buffer Flush=0D //=0D FlushWriteBuffer (VtdUnitBaseAddress);=0D =0D diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Inte= lVTdDmarPei.h b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/I= ntelVTdDmarPei.h index 7bed0a53..5ade9ec3 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDma= rPei.h +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDma= rPei.h @@ -21,7 +21,7 @@ typedef struct { VTD_ECAP_REG ECapReg;=0D BOOLEAN Is5LevelPaging;=0D UINT8 EnableQueuedInvalidation;=0D - UINT16 QueueSize;=0D + UINT16 QiDescLength;=0D QI_DESC *QiDesc;=0D UINT16 QiFreeHead;=0D UINTN FixedSecondLevelPagingEntry;=0D diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c= b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c index 61be2dcc..c7a56cf5 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c @@ -72,7 +72,7 @@ PerpareCacheInvalidationInterface ( UINT64 Reg64;=0D UINT32 Reg32;=0D =0D - if (mVtdUnitInformation[VtdIndex].VerReg.Bits.Major <=3D 6) {=0D + if (mVtdUnitInformation[VtdIndex].VerReg.Bits.Major <=3D 5) {=0D mVtdUnitInformation[VtdIndex].EnableQueuedInvalidation =3D 0;=0D DEBUG ((DEBUG_INFO, "Use Register-based Invalidation Interface for eng= ine [%d]\n", VtdIndex));=0D return EFI_SUCCESS;=0D --=20 2.26.2.windows.1