From: "Ard Biesheuvel" <ardb@kernel.org>
To: devel@edk2.groups.io
Cc: quic_llindhol@quicinc.com, sami.mujawar@arm.com,
Ard Biesheuvel <ardb@kernel.org>, Marc Zyngier <maz@kernel.org>,
Alexander Graf <graf@amazon.com>
Subject: [PATCH 0/7] ArmVirtPkg/ArmVirtQemu: avoid stores with MMU off
Date: Mon, 4 Jul 2022 19:52:45 +0200 [thread overview]
Message-ID: <20220704175252.4015120-1-ardb@kernel.org> (raw)
We currently do a substantial amount of processing before enabling the
MMU and caches, which is bad for performance, but also risky, as it
requires cache coherency to be managed by hand.
This also means that when running under virtualization, the hypervisor
must do a non-trivial amount of work to ensure that the host's cached
view of memory is consistent with the guest's uncached view.
So let's update the ArmVirtQemu early boot sequence to improve the
situation:
- instead of switching the MMU off and on again to meet
break-before-make (BBM) requirements when running at EL1, use two sets
of page tables and switch between then using different ASIDs;
- use a compile time generated ID map that covers the first bank of NOR
flash, the first MMIO region (for the UART), and the first 128 MiB of
DRAM, and switch to it straight out of reset.
The resulting build no longer performs any memory accesses via the data
side, and only relies on instruction fetches before the MMU is enabled.
Cc: Marc Zyngier <maz@kernel.org>
Cc: Alexander Graf <graf@amazon.com>
Ard Biesheuvel (7):
ArmPkg/ArmMmuLib: don't replace table entries with block entries
ArmPkg/ArmMmuLib: use shadow page tables for break-before-make at EL1
ArmPkg/ArmMmuLib: permit initial configuration with MMU enabled
ArmPlatformPkg/PrePeiCore: permit entry with the MMU enabled
ArmVirtPkg/ArmVirtQemu: implement ArmPlatformLib with static ID map
ArmVirtPkg/ArmVirtQemu: use first 128 MiB as permanent PEI memory
ArmVirtPkg/ArmVirtQemu: enable initial ID map at early boot
ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c | 3 +
ArmPkg/Include/Chipset/AArch64Mmu.h | 1 +
ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 162 ++++++++++++--------
ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S | 15 +-
ArmPlatformPkg/PrePeiCore/PrePeiCore.c | 22 +--
ArmVirtPkg/ArmVirtQemu.dsc | 10 +-
ArmVirtPkg/ArmVirtQemu.fdf | 2 +-
ArmVirtPkg/Library/ArmPlatformLibQemu/AArch64/ArmPlatformHelper.S | 111 ++++++++++++++
ArmVirtPkg/Library/ArmPlatformLibQemu/ArmPlatformLibQemu.c | 36 +++++
ArmVirtPkg/Library/ArmPlatformLibQemu/ArmPlatformLibQemu.inf | 36 +++++
ArmVirtPkg/Library/ArmPlatformLibQemu/IdMap.S | 57 +++++++
ArmVirtPkg/MemoryInitPei/MemoryInitPeim.c | 89 +++++++++++
ArmVirtPkg/MemoryInitPei/MemoryInitPeim.inf | 66 ++++++++
13 files changed, 530 insertions(+), 80 deletions(-)
create mode 100644 ArmVirtPkg/Library/ArmPlatformLibQemu/AArch64/ArmPlatformHelper.S
create mode 100644 ArmVirtPkg/Library/ArmPlatformLibQemu/ArmPlatformLibQemu.c
create mode 100644 ArmVirtPkg/Library/ArmPlatformLibQemu/ArmPlatformLibQemu.inf
create mode 100644 ArmVirtPkg/Library/ArmPlatformLibQemu/IdMap.S
create mode 100644 ArmVirtPkg/MemoryInitPei/MemoryInitPeim.c
create mode 100644 ArmVirtPkg/MemoryInitPei/MemoryInitPeim.inf
--
2.35.1
next reply other threads:[~2022-07-04 17:53 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-04 17:52 Ard Biesheuvel [this message]
2022-07-04 17:52 ` [PATCH 1/7] ArmPkg/ArmMmuLib: don't replace table entries with block entries Ard Biesheuvel
2022-07-04 17:52 ` [PATCH 2/7] ArmPkg/ArmMmuLib: use shadow page tables for break-before-make at EL1 Ard Biesheuvel
2022-07-04 17:52 ` [PATCH 3/7] ArmPkg/ArmMmuLib: permit initial configuration with MMU enabled Ard Biesheuvel
2022-07-04 17:52 ` [PATCH 4/7] ArmPlatformPkg/PrePeiCore: permit entry with the " Ard Biesheuvel
2022-07-04 17:52 ` [PATCH 5/7] ArmVirtPkg/ArmVirtQemu: implement ArmPlatformLib with static ID map Ard Biesheuvel
2022-07-04 17:52 ` [PATCH 6/7] ArmVirtPkg/ArmVirtQemu: use first 128 MiB as permanent PEI memory Ard Biesheuvel
2022-07-04 17:52 ` [PATCH 7/7] ArmVirtPkg/ArmVirtQemu: enable initial ID map at early boot Ard Biesheuvel
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