From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by mx.groups.io with SMTP id smtpd.web11.74764.1656957198560435812 for ; Mon, 04 Jul 2022 10:53:18 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=RTzgnOLw; spf=pass (domain: kernel.org, ip: 145.40.68.75, mailfrom: ardb@kernel.org) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 467EAB811EF; Mon, 4 Jul 2022 17:53:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AA3DFC341CD; Mon, 4 Jul 2022 17:53:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656957196; bh=i4pkumkcfdf//DDAB85zgxSkKMspren9OHJuspcHt8s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RTzgnOLwge532Ma9ozCsJJLOQ5+iyWKOYrovJYThKX/Bi0+rSwwXBmSSHxJojQDyl 8vDtiIK7kaHEqmHDDrBULqcw3DQ/FJJVaKMj+RrXltmws+BUZTY1Iwsid6cw2/oXlO n7HIJ8pSbLm4HxVfY6nGeKaC+Ao8sHOJ+M+fu4DCEoXsNCl4OcfBZRNlTzNY8DWZ2M NuLQmmY4XFAP1N9MB2wZUVG0iUyelU7Z1RXYoSjGNT848EC96oD7l2QPS4T6E74a1F 8iRaWs4/m+IF136muiqmQOsyoYoVEX99funBHZ4ww0Poaxf1MfjdQF3pfBlL+ka9BO g7rY9WsbGWosg== From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: quic_llindhol@quicinc.com, sami.mujawar@arm.com, Ard Biesheuvel , Marc Zyngier , Alexander Graf Subject: [PATCH 3/7] ArmPkg/ArmMmuLib: permit initial configuration with MMU enabled Date: Mon, 4 Jul 2022 19:52:48 +0200 Message-Id: <20220704175252.4015120-4-ardb@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220704175252.4015120-1-ardb@kernel.org> References: <20220704175252.4015120-1-ardb@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Permit the use of this library with the MMU and caches already enabled. This removes the need for any cache maintenance for coherency, and is generally better for robustness and performance, especially when running under virtualization. Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 30 +++++++++++--------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Libr= ary/ArmMmuLib/AArch64/ArmMmuLibCore.c index d5c19600dce8..8934ea6fd420 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -657,14 +657,16 @@ ArmConfigureMmu ( *TranslationTableSize =3D RootTableEntryCount * sizeof (UINT64);=0D }=0D =0D - //=0D - // Make sure we are not inadvertently hitting in the caches=0D - // when populating the page tables.=0D - //=0D - InvalidateDataCacheRange (=0D - TranslationTable,=0D - RootTableEntryCount * sizeof (UINT64)=0D - );=0D + if (!ArmMmuEnabled ()) {=0D + //=0D + // Make sure we are not inadvertently hitting in the caches=0D + // when populating the page tables.=0D + //=0D + InvalidateDataCacheRange (=0D + TranslationTable,=0D + RootTableEntryCount * sizeof (UINT64)=0D + );=0D + }=0D ZeroMem (TranslationTable, RootTableEntryCount * sizeof (UINT64));=0D =0D for (MemTab =3D MemoryTable; MemTab->Length !=3D 0; MemTab++) {=0D @@ -689,12 +691,14 @@ ArmConfigureMmu ( =0D ArmSetTTBR0 (TranslationTable);=0D =0D - ArmDisableAlignmentCheck ();=0D - ArmEnableStackAlignmentCheck ();=0D - ArmEnableInstructionCache ();=0D - ArmEnableDataCache ();=0D + if (!ArmMmuEnabled ()) {=0D + ArmDisableAlignmentCheck ();=0D + ArmEnableStackAlignmentCheck ();=0D + ArmEnableInstructionCache ();=0D + ArmEnableDataCache ();=0D =0D - ArmEnableMmu ();=0D + ArmEnableMmu ();=0D + }=0D =0D if (NumRootPages > 1) {=0D //=0D --=20 2.35.1