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Thu, 14 Jul 2022 16:50:42 +0000 From: "Sami Mujawar" To: CC: Sami Mujawar , , , , , , , , Subject: [PATCH v6 7/8] DynamicTablesPkg: Update ArmNameSpaceObjects for IORT Rev E.d Date: Thu, 14 Jul 2022 17:50:30 +0100 Message-ID: <20220714165031.42640-8-sami.mujawar@arm.com> X-Mailer: git-send-email 2.16.2.windows.1 In-Reply-To: <20220714165031.42640-1-sami.mujawar@arm.com> References: <20220714165031.42640-1-sami.mujawar@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-Correlation-Id: 17bf0d79-b632-457c-af13-08da65b91116 X-MS-TrafficTypeDiagnostic: AM0PR08MB3362:EE_|AM5EUR03FT006:EE_|PAXPR08MB6509:EE_ x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: G1tNv+wnK3scV2unpQSsckMGR5Kua7N1ReLNBun6C6Ztur1MwDEEfavy5PlA3LpYgBvknuhHzv6UunhgG72GPYLu6g1Y2XTqNPSi17stDSoGC2j6yUEw0VuvEwrkCoga84LebmmhWYwAbLpcyTdbYRMfTXUDQ6KCjvMuo5b4i8Bwzh/SiMqOnOjv0wf9zNEzn5OCgMBEaUU59zsm27jPX+0wB62ZS411jHsGwiHLk9rnKRkEPJV7BAJN+iFW9qmaAgTNFuNBv7j7ylGjznjABpabLImRBYACCj8yRdhczjZ/+GQWXypMqzbO0FgBd6MQtsISYz0aqyFMpCtHuQQcdCLOQM//csr1On8lu3bo3N4Qi5CdKr4TybThLvv4NcjQ76lxkbC/Pjxg27M0yN3Fz/nyCVcE7S5XpUN/RLaYRdIG4MI5ZSyX0/mfaruUD6cY1zQfEIvy1A4Zev4bF6tz/+zwSq19uAdoyTtpuxk9WMK7zcIEbQnsipmlml3KGxVHejXUT/+/8fE/pP4UH8fiXM+eH7z6Mu9Jc4AfHST1tgz8fwiHduAVuG6AOsPUL0c4kvHreZbI4z8880XS1Y27UWkuP3lC4aW9sZl4mWwUfn7c0r8KiXDNFBObjna2yXXxAe61kDyDboDPL02j20+RmKrxyCiCkA8isysKKEBX0z4Cbu6pD+VFdC5kQ0Y7utq+KZNOYPLPn4SGthVgXJcaz9PfrnXY89UdroCeyXhz+RYKjXLVxSrLPw/kApyYxRU02nv97wCzakz5wG+r1z0VwsQtLsktYu0HJ5nR3MbkT8XHvzjd4aeLsPodrlu/Z+CHlrykxMF8Ba885y0FjYl60fcR3xgw9OVXPtUEmZ1pfcOsBUfGn5wnvSfPj1ID4pHO1Ps8SGcbY0SkHG7GTav+0xGD7wtJzIMz5sYrN5kQxxY= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230016)(4636009)(396003)(136003)(376002)(39860400002)(346002)(46966006)(36840700001)(40470700004)(2906002)(336012)(41300700001)(83380400001)(356005)(44832011)(6666004)(70206006)(426003)(82740400003)(4326008)(47076005)(40480700001)(2616005)(186003)(7696005)(8936002)(966005)(15650500001)(86362001)(8676002)(70586007)(478600001)(82310400005)(19627235002)(5660300002)(1076003)(54906003)(81166007)(26005)(36860700001)(40460700003)(36756003)(316002)(6916009)(36900700001);DIR:OUT;SFP:1101; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jul 2022 16:51:15.5627 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 17bf0d79-b632-457c-af13-08da65b91116 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT006.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR08MB6509 Content-Type: text/plain Bugzilla: 3458 - Add support IORT Rev E.d specification updates (https://bugzilla.tianocore.org/show_bug.cgi?id=3458) The IO Remapping Table, Platform Design Document, Revision E.d, Feb 2022 (https://developer.arm.com/documentation/den0049/) introduces the following updates, collectively including the updates and errata fixes to Rev E, Rev E.a, Rev E.b, Rev E.c: - increments the IORT table revision to 5. - updates the node definition to add an 'Identifier' field. - adds definition of node type 6 - Reserved Memory Range node. - adds definition for Memory Range Descriptors. - adds flag to indicate PRI support for root complexes. - adds flag to indicate if the root complex supports forwarding of PASID information on translated transactions to the SMMU. - adds flag to indicate if the root complex supports PASID. - adds flags to define access privilege and attributes for the memory ranges. Therefore, update the Arm namespace objects to: - add Identifier field to IORT nodes. - introduce enums to represent RMR nodes and Memory Range descriptors. - add definition of node type 6 - Reserved Memory Range node. - add definition for Memory Range Descriptors. - add PASID capabilities and flags field to Root Complex node. Signed-off-by: Sami Mujawar --- Notes: v6: - No code change since v4. Re-sending with v6 series. [SAMI] v5: - No code change since v4. Re-sending with v5 series. [SAMI] v4: - Update ArmNameSpaceObjects to support IORT specification [SAMI] revision E.d. - Add PASID capabilities and flags field to Root Complex node. [SAMI] - Add flags to define access privilege and attributes for the [SAMI] memory ranges. - Update DynamicTablesPkg.ci.yaml to add PASID to the ignore [SAMI] list for the spell checker. v3: - Move Identifier field before Flags field in [PIERRE] CM_ARM_RMR_NODE. - Add description for CM_ARM_MEMORY_RANGE_DESCRIPTOR [PIERRE] field. - Updated based on review feedback. [SAMI] Ref: https://edk2.groups.io/g/devel/topic/83600723#76659 v2: - No code change since v1. Re-sending with v2 series. [SAMI] DynamicTablesPkg/DynamicTablesPkg.ci.yaml | 1 + DynamicTablesPkg/Include/ArmNameSpaceObjects.h | 66 +++++++++++++++++++- 2 files changed, 66 insertions(+), 1 deletion(-) diff --git a/DynamicTablesPkg/DynamicTablesPkg.ci.yaml b/DynamicTablesPkg/DynamicTablesPkg.ci.yaml index bfa282926e48c79ea748b12dee19a322197eaed1..5addf8626841fe35dd0d499a277cb7308787fee0 100644 --- a/DynamicTablesPkg/DynamicTablesPkg.ci.yaml +++ b/DynamicTablesPkg/DynamicTablesPkg.ci.yaml @@ -108,6 +108,7 @@ "lgreater", "lless", "MPIDR", + "PASID", "PERIPHBASE", "phandle", "pytool", diff --git a/DynamicTablesPkg/Include/ArmNameSpaceObjects.h b/DynamicTablesPkg/Include/ArmNameSpaceObjects.h index 91bef9bccd1978b0e396f423cff81e621b05e0ea..102e0f96beb22cc2b93c1525bef62cd4173774eb 100644 --- a/DynamicTablesPkg/Include/ArmNameSpaceObjects.h +++ b/DynamicTablesPkg/Include/ArmNameSpaceObjects.h @@ -1,6 +1,6 @@ /** @file - Copyright (c) 2017 - 2021, Arm Limited. All rights reserved.
+ Copyright (c) 2017 - 2022, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -61,6 +61,8 @@ typedef enum ArmObjectID { EArmObjLpiInfo, ///< 37 - Lpi Info EArmObjPciAddressMapInfo, ///< 38 - Pci Address Map Info EArmObjPciInterruptMapInfo, ///< 39 - Pci Interrupt Map Info + EArmObjRmr, ///< 40 - Reserved Memory Range Node + EArmObjMemoryRangeDescriptor, ///< 41 - Memory Range Descriptor EArmObjMax } EARM_OBJECT_ID; @@ -477,6 +479,9 @@ typedef struct CmArmItsGroupNode { UINT32 ItsIdCount; /// Reference token for the ITS identifier array CM_OBJECT_TOKEN ItsIdToken; + + /// Unique identifier for this node. + UINT32 Identifier; } CM_ARM_ITS_GROUP_NODE; /** A structure that describes the @@ -509,6 +514,9 @@ typedef struct CmArmNamedComponentNode { the entry in the namespace for this object. */ CHAR8 *ObjectName; + + /// Unique identifier for this node. + UINT32 Identifier; } CM_ARM_NAMED_COMPONENT_NODE; /** A structure that describes the @@ -537,6 +545,13 @@ typedef struct CmArmRootComplexNode { UINT32 PciSegmentNumber; /// Memory address size limit UINT8 MemoryAddressSize; + /// PASID capabilities + UINT16 PasidCapabilities; + /// Flags + UINT32 Flags; + + /// Unique identifier for this node. + UINT32 Identifier; } CM_ARM_ROOT_COMPLEX_NODE; /** A structure that describes the @@ -579,6 +594,9 @@ typedef struct CmArmSmmuV1SmmuV2Node { UINT32 SMMU_NSgCfgIrpt; /// SMMU_NSgCfgIrpt interrupt flags UINT32 SMMU_NSgCfgIrptFlags; + + /// Unique identifier for this node. + UINT32 Identifier; } CM_ARM_SMMUV1_SMMUV2_NODE; /** A structure that describes the @@ -615,6 +633,9 @@ typedef struct CmArmSmmuV3Node { UINT32 ProximityDomain; /// Index into the array of ID mapping UINT32 DeviceIdMappingIndex; + + /// Unique identifier for this node. + UINT32 Identifier; } CM_ARM_SMMUV3_NODE; /** A structure that describes the @@ -639,6 +660,9 @@ typedef struct CmArmPmcgNode { /// Reference token for the IORT node associated with this node CM_OBJECT_TOKEN ReferenceToken; + + /// Unique identifier for this node. + UINT32 Identifier; } CM_ARM_PMCG_NODE; /** A structure that describes the @@ -1006,6 +1030,46 @@ typedef struct CmArmPciInterruptMapInfo { CM_ARM_GENERIC_INTERRUPT IntcInterrupt; } CM_ARM_PCI_INTERRUPT_MAP_INFO; +/** A structure that describes the + RMR node for the Platform. + + ID: EArmObjRmr +*/ +typedef struct CmArmRmrNode { + /// An unique token used to identify this object + CM_OBJECT_TOKEN Token; + /// Number of ID mappings + UINT32 IdMappingCount; + /// Reference token for the ID mapping array + CM_OBJECT_TOKEN IdMappingToken; + + /// Unique identifier for this node. + UINT32 Identifier; + + /// Reserved Memory Range flags. + UINT32 Flags; + + /// Memory range descriptor count. + UINT32 MemRangeDescCount; + /// Reference token for the Memory Range descriptor array + CM_OBJECT_TOKEN MemRangeDescToken; +} CM_ARM_RMR_NODE; + +/** A structure that describes the + Memory Range descriptor. + + ID: EArmObjMemoryRangeDescriptor +*/ +typedef struct CmArmRmrDescriptor { + /// Base address of Reserved Memory Range, + /// aligned to a page size of 64K. + UINT64 BaseAddress; + + /// Length of the Reserved Memory range. + /// Must be a multiple of the page size of 64K. + UINT64 Length; +} CM_ARM_MEMORY_RANGE_DESCRIPTOR; + #pragma pack() #endif // ARM_NAMESPACE_OBJECTS_H_ -- 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'