From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mx.groups.io with SMTP id smtpd.web12.913.1657829087731546366 for ; Thu, 14 Jul 2022 13:04:47 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=LxLnrMyz; spf=pass (domain: intel.com, ip: 134.134.136.126, mailfrom: chasel.chiu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1657829087; x=1689365087; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=PTiQDcXQRDaZthjdZbgaWyR4UzuMf97+U5v99BC/LLI=; b=LxLnrMyz16wHdsOSKYsPD9oSF9WdxweFhLOWA8R0HmdwEhxaJf6bXBWe ZTFqEroz+KylPQXCXhlvfjn+ff5f7XJQYueWTB6lnUM5u01MN0ERUcgfF evCERiJzfBp/AzddY2XlmqsW7p57hDuk2kugFXNShlfXzMwQ41VyqK5f5 mGmzykDQJ4qBRHohJm+pBSm0SW02Hzm9UHqJj7Bq+roFex4hhO/n4fgLA sS7LBgBQZhFUgJ3SLIytgQbm4ZQ1b//x+l8xaFJhn6KJHgNgxX+48sJz5 YDJSZwJhqkjIn9UTSKSdc936+YLAeUv7gAsN9xxeoIoVuDNfQx0HsfAbF g==; X-IronPort-AV: E=McAfee;i="6400,9594,10408"; a="268645410" X-IronPort-AV: E=Sophos;i="5.92,272,1650956400"; d="scan'208";a="268645410" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2022 13:04:46 -0700 X-IronPort-AV: E=Sophos;i="5.92,272,1650956400"; d="scan'208";a="654020125" Received: from cpalit-mobl.amr.corp.intel.com (HELO cchiu4-mobl.gar.corp.intel.com) ([10.212.195.253]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2022 13:04:45 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Hongbin1 Zhang , Nate DeSimone , Star Zeng , Chasel Chiu Subject: [PATCH] IntelFsp2Pkg/FspSecCore: Add FSP-I API for SMM support. Date: Thu, 14 Jul 2022 13:04:28 -0700 Message-Id: <20220714200428.1989-1-chasel.chiu@intel.com> X-Mailer: git-send-email 2.35.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Hongbin1 Zhang REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3993 Add FSP-I API entry point for SMM support. Cc: Nate DeSimone Cc: Star Zeng Signed-off-by: Chasel Chiu Signed-off-by: Hongbin1 Zhang --- IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 13 +++++++++++++ IntelFsp2Pkg/FspSecCore/FspSecCoreI.inf | 54 ++++++++++++++++++++++= ++++++++++++++++++++++++++++++++ IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryI.nasm | 44 ++++++++++++++++++++++= ++++++++++++++++++++++ IntelFsp2Pkg/FspSecCore/X64/FspApiEntryI.nasm | 44 ++++++++++++++++++++++= ++++++++++++++++++++++ IntelFsp2Pkg/Include/FspEas/FspApi.h | 57 ++++++++++++++++++++++= ++++++++++++++++------------------- IntelFsp2Pkg/Include/FspGlobalData.h | 53 ++++++++++++++++++++++= ++++++------------------------- IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 22 +++++++++++++++------- IntelFsp2Pkg/IntelFsp2Pkg.dsc | 1 + IntelFsp2Pkg/Tools/GenCfgOpt.py | 26 ++++++++++++++++------= ---- IntelFsp2Pkg/Tools/SplitFspBin.py | 6 +++--- 10 files changed, 256 insertions(+), 64 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c b/IntelFsp2Pkg/FspSecCo= re/SecFspApiChk.c index e22a88cc84..35d223a404 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c +++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c @@ -71,6 +71,19 @@ FspApiCallingCheck ( Status =3D EFI_INVALID_PARAMETER;=0D }=0D }=0D + } else if (ApiIdx =3D=3D FspSmmInitApiIndex) {=0D + //=0D + // FspSmmInitApiIndex check=0D + //=0D + if ((FspData =3D=3D NULL) || ((UINTN)FspData =3D=3D MAX_ADDRESS) || ((= UINTN)FspData =3D=3D MAX_UINT32)) {=0D + Status =3D EFI_UNSUPPORTED;=0D + } else {=0D + if (FspData->Signature !=3D FSP_GLOBAL_DATA_SIGNATURE) {=0D + Status =3D EFI_UNSUPPORTED;=0D + } else if (EFI_ERROR (FspUpdSignatureCheck (FspSmmInitApiIndex, ApiP= aram))) {=0D + Status =3D EFI_INVALID_PARAMETER;=0D + }=0D + }=0D } else {=0D Status =3D EFI_UNSUPPORTED;=0D }=0D diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreI.inf b/IntelFsp2Pkg/FspSecC= ore/FspSecCoreI.inf new file mode 100644 index 0000000000..d31576c00b --- /dev/null +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreI.inf @@ -0,0 +1,54 @@ +## @file=0D +# Sec Core for FSP=0D +#=0D +# Copyright (c) 2022, Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D FspSecCoreI=0D + FILE_GUID =3D 558782b5-782d-415e-ab9e-0ceb79dc3425= =0D + MODULE_TYPE =3D SEC=0D + VERSION_STRING =3D 1.0=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64=0D +#=0D +=0D +[Sources]=0D + SecFspApiChk.c=0D + SecFsp.h=0D +=0D +[Sources.X64]=0D + X64/FspApiEntryI.nasm=0D + X64/FspApiEntryCommon.nasm=0D + X64/FspHelper.nasm=0D +=0D +[Sources.IA32]=0D + Ia32/FspApiEntryI.nasm=0D + Ia32/FspApiEntryCommon.nasm=0D + Ia32/FspHelper.nasm=0D +=0D +[Binaries.Ia32]=0D + RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + IntelFsp2Pkg/IntelFsp2Pkg.dec=0D +=0D +[LibraryClasses]=0D + BaseMemoryLib=0D + DebugLib=0D + BaseLib=0D + PciCf8Lib=0D + SerialPortLib=0D + FspSwitchStackLib=0D + FspCommonLib=0D + FspSecPlatformLib=0D +=0D +=0D diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryI.nasm b/IntelFsp2Pkg/= FspSecCore/Ia32/FspApiEntryI.nasm new file mode 100644 index 0000000000..e9365d6832 --- /dev/null +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryI.nasm @@ -0,0 +1,44 @@ +;; @file=0D +; Provide FSP API entry points.=0D +;=0D +; Copyright (c) 2022, Intel Corporation. All rights reserved.
=0D +; SPDX-License-Identifier: BSD-2-Clause-Patent=0D +;;=0D +=0D + SECTION .text=0D +=0D +;=0D +; Following functions will be provided in C=0D +;=0D +extern ASM_PFX(FspApiCommon)=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; FspApiCommonContinue API=0D +;=0D +; This is the FSP API common entry point to resume the FSP execution=0D +;=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(FspApiCommonContinue)=0D +ASM_PFX(FspApiCommonContinue):=0D + jmp $=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; FspSmmInit API=0D +;=0D +; This FSP API will notify the FSP about the different phases in the boot= =0D +; process=0D +;=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(FspSmmInitApi)=0D +ASM_PFX(FspSmmInitApi):=0D + mov eax, 7 ; FSP_API_INDEX.FspSmmInitApiIndex=0D + jmp ASM_PFX(FspApiCommon)=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; Module Entrypoint API=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(_ModuleEntryPoint)=0D +ASM_PFX(_ModuleEntryPoint):=0D + jmp $=0D + ; Add reference to APIs so that it will not be optimized by compiler=0D + jmp ASM_PFX(FspSmmInitApi)=0D diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryI.nasm b/IntelFsp2Pkg/F= spSecCore/X64/FspApiEntryI.nasm new file mode 100644 index 0000000000..e9365d6832 --- /dev/null +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryI.nasm @@ -0,0 +1,44 @@ +;; @file=0D +; Provide FSP API entry points.=0D +;=0D +; Copyright (c) 2022, Intel Corporation. All rights reserved.
=0D +; SPDX-License-Identifier: BSD-2-Clause-Patent=0D +;;=0D +=0D + SECTION .text=0D +=0D +;=0D +; Following functions will be provided in C=0D +;=0D +extern ASM_PFX(FspApiCommon)=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; FspApiCommonContinue API=0D +;=0D +; This is the FSP API common entry point to resume the FSP execution=0D +;=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(FspApiCommonContinue)=0D +ASM_PFX(FspApiCommonContinue):=0D + jmp $=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; FspSmmInit API=0D +;=0D +; This FSP API will notify the FSP about the different phases in the boot= =0D +; process=0D +;=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(FspSmmInitApi)=0D +ASM_PFX(FspSmmInitApi):=0D + mov eax, 7 ; FSP_API_INDEX.FspSmmInitApiIndex=0D + jmp ASM_PFX(FspApiCommon)=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; Module Entrypoint API=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(_ModuleEntryPoint)=0D +ASM_PFX(_ModuleEntryPoint):=0D + jmp $=0D + ; Add reference to APIs so that it will not be optimized by compiler=0D + jmp ASM_PFX(FspSmmInitApi)=0D diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h b/IntelFsp2Pkg/Include/Fs= pEas/FspApi.h index b36bc2b9ae..1d6c2fb63d 100644 --- a/IntelFsp2Pkg/Include/FspEas/FspApi.h +++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h @@ -135,18 +135,18 @@ typedef struct { ///=0D /// Revision of the structure is 2 for this version of the specification= .=0D ///=0D - UINT8 Revision;=0D - UINT8 Reserved[3];=0D + UINT8 Revision;=0D + UINT8 Reserved[3];=0D ///=0D /// Length of the structure in bytes. The current value for this field i= s 32.=0D ///=0D - UINT32 Length;=0D + UINT32 Length;=0D ///=0D /// FspDebugHandler Optional debug handler for the bootloader to receive= debug messages=0D /// occurring during FSP execution.=0D ///=0D - EFI_PHYSICAL_ADDRESS FspDebugHandler;=0D - UINT8 Reserved1[16];=0D + EFI_PHYSICAL_ADDRESS FspDebugHandler;=0D + UINT8 Reserved1[16];=0D } FSPT_ARCH2_UPD;=0D =0D ///=0D @@ -197,37 +197,37 @@ typedef struct { ///=0D /// Revision of the structure is 3 for this version of the specification= .=0D ///=0D - UINT8 Revision;=0D - UINT8 Reserved[3];=0D + UINT8 Revision;=0D + UINT8 Reserved[3];=0D ///=0D /// Length of the structure in bytes. The current value for this field i= s 64.=0D ///=0D - UINT32 Length;=0D + UINT32 Length;=0D ///=0D /// Pointer to the temporary stack base address to be=0D /// consumed inside FspMemoryInit() API.=0D ///=0D - EFI_PHYSICAL_ADDRESS StackBase;=0D + EFI_PHYSICAL_ADDRESS StackBase;=0D ///=0D /// Temporary stack size to be consumed inside=0D /// FspMemoryInit() API.=0D ///=0D - UINT64 StackSize;=0D + UINT64 StackSize;=0D ///=0D /// Size of memory to be reserved by FSP below "top=0D /// of low usable memory" for bootloader usage.=0D ///=0D - UINT32 BootLoaderTolumSize;=0D + UINT32 BootLoaderTolumSize;=0D ///=0D /// Current boot mode.=0D ///=0D - UINT32 BootMode;=0D + UINT32 BootMode;=0D ///=0D /// Optional event handler for the bootloader to be informed of events o= ccurring during FSP execution.=0D /// This value is only valid if Revision is >=3D 2.=0D ///=0D - EFI_PHYSICAL_ADDRESS FspEventHandler;=0D - UINT8 Reserved1[24];=0D + EFI_PHYSICAL_ADDRESS FspEventHandler;=0D + UINT8 Reserved1[24];=0D } FSPM_ARCH2_UPD;=0D =0D ///=0D @@ -266,18 +266,18 @@ typedef struct { ///=0D /// Revision of the structure is 2 for this version of the specification= .=0D ///=0D - UINT8 Revision;=0D - UINT8 Reserved[3];=0D + UINT8 Revision;=0D + UINT8 Reserved[3];=0D ///=0D /// Length of the structure in bytes. The current value for this field i= s 32.=0D ///=0D - UINT32 Length;=0D + UINT32 Length;=0D ///=0D /// FspEventHandler Optional event handler for the bootloader to be info= rmed of events=0D /// occurring during FSP execution.=0D ///=0D - EFI_PHYSICAL_ADDRESS FspEventHandler;=0D - UINT8 Reserved1[16];=0D + EFI_PHYSICAL_ADDRESS FspEventHandler;=0D + UINT8 Reserved1[16];=0D } FSPS_ARCH2_UPD;=0D =0D ///=0D @@ -609,4 +609,23 @@ EFI_STATUS IN FSP_MULTI_PHASE_PARAMS *MultiPhaseSiInitParamPtr=0D );=0D =0D +/**=0D + This FSP API initializes SMM and provide any OS runtime silicon services= ,=0D + including Reliability, Availability, and Serviceability (RAS) features i= mplemented by the CPU.=0D +=0D + @param[in] FspiUpdDataPtr Pointer to the FSPI_UPD data structure.=0D + If NULL, FSP will use the default paramete= rs.=0D +=0D + @retval EFI_SUCCESS FSP execution environment was initia= lized successfully.=0D + @retval EFI_INVALID_PARAMETER Input parameters are invalid.=0D + @retval EFI_UNSUPPORTED The FSP calling conditions were not = met.=0D + @retval EFI_DEVICE_ERROR FSP initialization failed.=0D + @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status co= des will not be returned during S3.=0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *FSP_SMM_INIT)(=0D + IN VOID *FspiUpdDataPtr=0D + );=0D +=0D #endif=0D diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h b/IntelFsp2Pkg/Include/Fs= pGlobalData.h index 445540abfa..697b20ed4c 100644 --- a/IntelFsp2Pkg/Include/FspGlobalData.h +++ b/IntelFsp2Pkg/Include/FspGlobalData.h @@ -10,9 +10,9 @@ =0D #include =0D =0D -#define FSP_IN_API_MODE 0=0D -#define FSP_IN_DISPATCH_MODE 1=0D -#define FSP_GLOBAL_DATA_VERSION 1=0D +#define FSP_IN_API_MODE 0=0D +#define FSP_IN_DISPATCH_MODE 1=0D +#define FSP_GLOBAL_DATA_VERSION 1=0D =0D #pragma pack(1)=0D =0D @@ -24,16 +24,17 @@ typedef enum { TempRamExitApiIndex,=0D FspSiliconInitApiIndex,=0D FspMultiPhaseSiInitApiIndex,=0D + FspSmmInitApiIndex,=0D FspApiIndexMax=0D } FSP_API_INDEX;=0D =0D typedef struct {=0D - VOID *DataPtr;=0D - UINTN MicrocodeRegionBase;=0D - UINTN MicrocodeRegionSize;=0D - UINTN CodeRegionBase;=0D - UINTN CodeRegionSize;=0D - UINTN Reserved;=0D + VOID *DataPtr;=0D + UINTN MicrocodeRegionBase;=0D + UINTN MicrocodeRegionSize;=0D + UINTN CodeRegionBase;=0D + UINTN CodeRegionSize;=0D + UINTN Reserved;=0D } FSP_PLAT_DATA;=0D =0D #define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D')= =0D @@ -41,28 +42,28 @@ typedef struct { #define FSP_PERFORMANCE_DATA_TIMER_MASK 0xFFFFFFFFFFFFFF=0D =0D typedef struct {=0D - UINT32 Signature;=0D - UINT8 Version;=0D - UINT8 Reserved1[3];=0D + UINT32 Signature;=0D + UINT8 Version;=0D + UINT8 Reserved1[3];=0D ///=0D /// Offset 0x08=0D ///=0D - UINTN CoreStack;=0D - UINTN Reserved2;=0D + UINTN CoreStack;=0D + UINTN Reserved2;=0D ///=0D /// IA32: Offset 0x10; X64: Offset 0x18=0D ///=0D - UINT32 StatusCode;=0D - UINT8 ApiIdx;=0D + UINT32 StatusCode;=0D + UINT8 ApiIdx;=0D ///=0D /// 0: FSP in API mode; 1: FSP in DISPATCH mode=0D ///=0D - UINT8 FspMode;=0D - UINT8 OnSeparateStack;=0D - UINT8 Reserved3;=0D - UINT32 NumberOfPhases;=0D - UINT32 PhasesExecuted;=0D - UINT32 Reserved4[8];=0D + UINT8 FspMode;=0D + UINT8 OnSeparateStack;=0D + UINT8 Reserved3;=0D + UINT32 NumberOfPhases;=0D + UINT32 PhasesExecuted;=0D + UINT32 Reserved4[8];=0D ///=0D /// IA32: Offset 0x40; X64: Offset 0x48=0D /// Start of UINTN and pointer section=0D @@ -75,21 +76,23 @@ typedef struct { VOID *TempRamInitUpdPtr;=0D VOID *MemoryInitUpdPtr;=0D VOID *SiliconInitUpdPtr;=0D + VOID *SmmInitUpdPtr;=0D ///=0D - /// IA32: Offset 0x64; X64: Offset 0x90=0D + /// IA32: Offset 0x68; X64: Offset 0x98=0D /// To store function parameters pointer=0D /// so it can be retrieved after stack switched.=0D ///=0D VOID *FunctionParameterPtr;=0D FSP_INFO_HEADER *FspInfoHeader;=0D VOID *UpdDataPtr;=0D + UINTN Reserved5;=0D ///=0D /// End of UINTN and pointer section=0D ///=0D - UINT8 Reserved5[16];=0D + UINT8 Reserved6[16];=0D UINT32 PerfSig;=0D UINT16 PerfLen;=0D - UINT16 Reserved6;=0D + UINT16 Reserved7;=0D UINT32 PerfIdx;=0D UINT64 PerfData[32];=0D } FSP_GLOBAL_DATA;=0D diff --git a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h b/IntelFsp2Pkg/Inclu= de/Guid/FspHeaderFile.h index c660defac3..c7fb63168f 100644 --- a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h +++ b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h @@ -26,13 +26,13 @@ =0D #define FSP_INFO_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'H')=0D =0D -#define IMAGE_ATTRIBUTE_GRAPHICS_SUPPORT BIT0=0D -#define IMAGE_ATTRIBUTE_DISPATCH_MODE_SUPPORT BIT1=0D -#define IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT BIT2=0D -#define FSP_IA32 0=0D -#define FSP_X64 1=0D +#define IMAGE_ATTRIBUTE_GRAPHICS_SUPPORT BIT0=0D +#define IMAGE_ATTRIBUTE_DISPATCH_MODE_SUPPORT BIT1=0D +#define IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT BIT2=0D +#define FSP_IA32 0=0D +#define FSP_X64 1=0D =0D -#pragma pack(1)=0D + #pragma pack(1)=0D =0D ///=0D /// FSP Information Header as described in FSP v2.0 Spec section 5.1.1.=0D @@ -159,6 +159,14 @@ typedef struct { /// Byte 0x4E: Reserved4.=0D ///=0D UINT16 Reserved4;=0D + ///=0D + /// Byte 0x50: Offset for the API for the Multi-Phase memory initializat= ion.=0D + ///=0D + UINT32 FspMultiPhaseMemInitEntryOffset;=0D + ///=0D + /// Byte 0x54: Offset for the API to initialize SMM.=0D + ///=0D + UINT32 FspSmmInitEntryOffset;=0D } FSP_INFO_HEADER;=0D =0D ///=0D @@ -240,7 +248,7 @@ typedef struct { // UINT32 PatchData[];=0D } FSP_PATCH_TABLE;=0D =0D -#pragma pack()=0D + #pragma pack()=0D =0D extern EFI_GUID gFspHeaderFileGuid;=0D =0D diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dsc b/IntelFsp2Pkg/IntelFsp2Pkg.dsc index 7cf7e88245..b2d7867880 100644 --- a/IntelFsp2Pkg/IntelFsp2Pkg.dsc +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dsc @@ -68,6 +68,7 @@ IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf=0D IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf=0D IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf=0D + IntelFsp2Pkg/FspSecCore/FspSecCoreI.inf=0D IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf=0D IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.inf=0D =0D diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py b/IntelFsp2Pkg/Tools/GenCfgOpt= .py index c4fb1f1bb2..128b896592 100644 --- a/IntelFsp2Pkg/Tools/GenCfgOpt.py +++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py @@ -953,8 +953,8 @@ EndList return NoFileChange=0D =0D def CreateSplitUpdTxt (self, UpdTxtFile):=0D - GuidList =3D ['FSP_T_UPD_TOOL_GUID','FSP_M_UPD_TOOL_GUID','FSP_S_U= PD_TOOL_GUID']=0D - SignatureList =3D ['0x545F', '0x4D5F','0x535F'] # _T, _M, = and _S signature for FSPT, FSPM, FSPS=0D + GuidList =3D ['FSP_T_UPD_TOOL_GUID','FSP_M_UPD_TOOL_GUID','FSP_S_U= PD_TOOL_GUID','FSP_I_UPD_TOOL_GUID']=0D + SignatureList =3D ['0x545F', '0x4D5F','0x535F','0x495F'] # = _T, _M, _S and _I signature for FSPT, FSPM, FSPS, FSPI=0D for Index in range(len(GuidList)):=0D UpdTxtFile =3D ''=0D FvDir =3D self._FvDir=0D @@ -1288,19 +1288,21 @@ EndList Chars.append(chr(Value & 0xFF))=0D Value =3D Value >> 8=0D SignatureStr =3D ''.join(Chars)=0D - # Signature will be _T / _M / _S for FSPT / FSPM / FSPS acc= ordingly=0D + # Signature will be _T / _M / _S / _I for FSPT / FSPM / FSP= S /FSPI accordingly=0D if '_T' in SignatureStr[6:6+2]:=0D TxtBody.append("#define FSPT_UPD_SIGNATURE = %s /* '%s' */\n\n" % (Item['value'], SignatureStr))=0D elif '_M' in SignatureStr[6:6+2]:=0D TxtBody.append("#define FSPM_UPD_SIGNATURE = %s /* '%s' */\n\n" % (Item['value'], SignatureStr))=0D elif '_S' in SignatureStr[6:6+2]:=0D TxtBody.append("#define FSPS_UPD_SIGNATURE = %s /* '%s' */\n\n" % (Item['value'], SignatureStr))=0D + elif '_I' in SignatureStr[6:6+2]:=0D + TxtBody.append("#define FSPI_UPD_SIGNATURE = %s /* '%s' */\n\n" % (Item['value'], SignatureStr))=0D TxtBody.append("\n")=0D =0D for Region in ['UPD']:=0D UpdOffsetTable =3D []=0D - UpdSignature =3D ['0x545F', '0x4D5F', '0x535F'] #['_T', '_M'= , '_S'] signature for FSPT, FSPM, FSPS=0D - UpdStructure =3D ['FSPT_UPD', 'FSPM_UPD', 'FSPS_UPD']=0D + UpdSignature =3D ['0x545F', '0x4D5F', '0x535F', '0x495F'] #[= '_T', '_M', '_S', '_I'] signature for FSPT, FSPM, FSPS, FSPI=0D + UpdStructure =3D ['FSPT_UPD', 'FSPM_UPD', 'FSPS_UPD', 'FSPI_UP= D']=0D for Item in self._CfgItemList:=0D if Item["cname"] =3D=3D 'Signature' and Item["value"][0:6]= in UpdSignature:=0D Item["offset"] =3D 0 # re-initialize offset to 0 when = new UPD structure starting=0D @@ -1393,11 +1395,12 @@ EndList HeaderTFileName =3D 'FsptUpd.h'=0D HeaderMFileName =3D 'FspmUpd.h'=0D HeaderSFileName =3D 'FspsUpd.h'=0D + HeaderIFileName =3D 'FspiUpd.h'=0D =0D - UpdRegionCheck =3D ['FSPT', 'FSPM', 'FSPS'] # FSPX_UPD_REGION= =0D - UpdConfigCheck =3D ['FSP_T', 'FSP_M', 'FSP_S'] # FSP_X_CONFIG, FS= P_X_TEST_CONFIG, FSP_X_RESTRICTED_CONFIG=0D - UpdSignatureCheck =3D ['FSPT_UPD_SIGNATURE', 'FSPM_UPD_SIGNATURE',= 'FSPS_UPD_SIGNATURE']=0D - ExcludedSpecificUpd =3D ['FSPT_ARCH_UPD', 'FSPM_ARCH_UPD', 'FSPS_A= RCH_UPD']=0D + UpdRegionCheck =3D ['FSPT', 'FSPM', 'FSPS', 'FSPI'] # FSPX_UPD= _REGION=0D + UpdConfigCheck =3D ['FSP_T', 'FSP_M', 'FSP_S', 'FSP_I'] # FSP_X_C= ONFIG, FSP_X_TEST_CONFIG, FSP_X_RESTRICTED_CONFIG=0D + UpdSignatureCheck =3D ['FSPT_UPD_SIGNATURE', 'FSPM_UPD_SIGNATURE',= 'FSPS_UPD_SIGNATURE', 'FSPI_UPD_SIGNATURE']=0D + ExcludedSpecificUpd =3D ['FSPT_ARCH_UPD', 'FSPM_ARCH_UPD', 'FSPS_A= RCH_UPD', 'FSPI_ARCH_UPD']=0D ExcludedSpecificUpd1 =3D ['FSPT_ARCH2_UPD', 'FSPM_ARCH2_UPD', 'FSP= S_ARCH2_UPD']=0D =0D IncLines =3D []=0D @@ -1420,6 +1423,9 @@ EndList elif UpdRegionCheck[item] =3D=3D 'FSPS':=0D HeaderFd =3D open(os.path.join(FvDir, HeaderSFileName), "w= ")=0D FileBase =3D os.path.basename(os.path.join(FvDir, HeaderSF= ileName))=0D + elif UpdRegionCheck[item] =3D=3D 'FSPI':=0D + HeaderFd =3D open(os.path.join(FvDir, HeaderIFileName), "w= ")=0D + FileBase =3D os.path.basename(os.path.join(FvDir, HeaderIF= ileName))=0D FileName =3D FileBase.replace(".", "_").upper()=0D HeaderFd.write("%s\n" % (__copyright_h__ % date.today().year= ))=0D HeaderFd.write("#ifndef __%s__\n" % FileName)=0D @@ -1696,7 +1702,7 @@ EndList =0D =0D def Usage():=0D - print ("GenCfgOpt Version 0.57")=0D + print ("GenCfgOpt Version 0.58")=0D print ("Usage:")=0D print (" GenCfgOpt UPDTXT PlatformDscFile BuildFvDir = [-D Macros]")=0D print (" GenCfgOpt HEADER PlatformDscFile BuildFvDir InputHFile = [-D Macros]")=0D diff --git a/IntelFsp2Pkg/Tools/SplitFspBin.py b/IntelFsp2Pkg/Tools/SplitFs= pBin.py index f9151b5afd..317d9c1fa0 100644 --- a/IntelFsp2Pkg/Tools/SplitFspBin.py +++ b/IntelFsp2Pkg/Tools/SplitFspBin.py @@ -1,6 +1,6 @@ ## @ SplitFspBin.py=0D #=0D -# Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
=0D +# Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.
=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D ##=0D @@ -492,7 +492,7 @@ class FspImage: self.FihOffset =3D fihoff=0D self.Offset =3D offset=0D self.FvIdxList =3D []=0D - self.Type =3D "XTMSXXXXOXXXXXXX"[(fih.ComponentAttribute >> 1= 2) & 0x0F]=0D + self.Type =3D "XTMSIXXXXOXXXXXXX"[(fih.ComponentAttribute >> = 12) & 0x0F]=0D self.PatchList =3D patch=0D self.PatchList.append(fihoff + 0x1C)=0D =0D @@ -869,7 +869,7 @@ def main (): parser_rebase =3D subparsers.add_parser('rebase', help=3D'rebase a F= SP into a new base address')=0D parser_rebase.set_defaults(which=3D'rebase')=0D parser_rebase.add_argument('-f', '--fspbin' , dest=3D'FspBinary', ty= pe=3Dstr, help=3D'FSP binary file path', required =3D True)=0D - parser_rebase.add_argument('-c', '--fspcomp', choices=3D['t','m','s',= 'o'], nargs=3D'+', dest=3D'FspComponent', type=3Dstr, help=3D'FSP componen= t to rebase', default =3D "['t']", required =3D True)=0D + parser_rebase.add_argument('-c', '--fspcomp', choices=3D['t','m','s',= 'o','i'], nargs=3D'+', dest=3D'FspComponent', type=3Dstr, help=3D'FSP comp= onent to rebase', default =3D "['t']", required =3D True)=0D parser_rebase.add_argument('-b', '--newbase', dest=3D'FspBase', nargs= =3D'+', type=3Dstr, help=3D'Rebased FSP binary file name', default =3D '', = required =3D True)=0D parser_rebase.add_argument('-o', '--outdir' , dest=3D'OutputDir', ty= pe=3Dstr, help=3D'Output directory path', default =3D '.')=0D parser_rebase.add_argument('-n', '--outfile', dest=3D'OutputFile', ty= pe=3Dstr, help=3D'Rebased FSP binary file name', default =3D '')=0D --=20 2.35.0.windows.1