From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web12.27079.1658150325580236005 for ; Mon, 18 Jul 2022 06:18:46 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=Vbuag9Wz; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: ray.ni@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658150326; x=1689686326; h=from:to:subject:date:message-id:mime-version: content-transfer-encoding; bh=x5Hv6j6hUz1yhf31y0AqicRAhZHXNlFNpWqspqb+pA4=; b=Vbuag9WzoSvxl15mXeJiEyE1+VuUIr2L0qcDt1LhPNAR8Nn75jSZtLxC mn28+UdrscFL1TlXfdU0MD5O05DQ6dh2kKbzQN+UNt825k5ooTxLMPOtK ws5Xh9XzrNQrtJ3D8va18S3sDsm1ZSuRqP7/DMykybJ5IKBJr8wCpct+q VUXYc6pVjP+YA3kVzwEE/nFe/+Nye5kvQX7HW5vqDCEdUEfuKvaTRfKVo vRjP7iHnJoQRtriayzCtzr9IJBAIueYl5/XikFOlD5XutmbF5GBnaz0TM OdKtQ2UdfjQzv0rKU7dzrwCx/rakMmC/mIW0sZMEZf5e8TuB5dH7KqO3O Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10411"; a="287363883" X-IronPort-AV: E=Sophos;i="5.92,281,1650956400"; d="scan'208";a="287363883" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jul 2022 06:18:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,281,1650956400"; d="scan'208";a="624724932" Received: from shwdeopenlab706.ccr.corp.intel.com ([10.239.183.102]) by orsmga008.jf.intel.com with ESMTP; 18 Jul 2022 06:18:38 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Subject: [PATCH 00/10] UefiCpuPkg: Create CpuPageTableLib for manipulating X86 paging structs Date: Mon, 18 Jul 2022 21:18:21 +0800 Message-Id: <20220718131831.660-1-ray.ni@intel.com> X-Mailer: git-send-email 2.35.1.windows.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Ray Ni (10): UefiCpuPkg: Create CpuPageTableLib for manipulating X86 paging structs UefiCpuPkg/CpuPageTableLib: Return error on invalid parameters CpuPageTableLib: Fix a bug when a bit is 1 in Attribute, 0 in Mask CpuPageTableLib: Refactor the logic CpuPageTableLib: Split the page entry when LA is aligned but PA is not CpuPageTableLib: Avoid treating non-leaf entry as leaf one CpuPageTableLib: Fix parent attributes are not inherited properly CpuPageTableLib: Fix a bug to avoid unnecessary changing to page table CpuPageTableLib: Fix bug that wrongly requires extra size for mapping CpuPageTableLib: define IA32_PAGE_LEVEL enum type internally UefiCpuPkg/Include/Library/CpuPageTableLib.h | 129 ++++ .../Library/CpuPageTableLib/CpuPageTable.h | 230 ++++++ .../CpuPageTableLib/CpuPageTableLib.inf | 35 + .../Library/CpuPageTableLib/CpuPageTableMap.c | 690 ++++++++++++++++++ .../CpuPageTableLib/CpuPageTableParse.c | 330 +++++++++ UefiCpuPkg/UefiCpuPkg.dec | 3 + UefiCpuPkg/UefiCpuPkg.dsc | 4 +- 7 files changed, 1420 insertions(+), 1 deletion(-) create mode 100644 UefiCpuPkg/Include/Library/CpuPageTableLib.h create mode 100644 UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h create mode 100644 UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf create mode 100644 UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c create mode 100644 UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableParse.c -- 2.35.1.windows.2