From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web08.27105.1658150328221476289 for ; Mon, 18 Jul 2022 06:18:52 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=k6MiCbWG; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: ray.ni@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658150332; x=1689686332; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+7QfxFpiNKFyXn1ty24HCI7CyG9PtPpu/EB1TxuQb50=; b=k6MiCbWGJSBXFa1mQF+h+zmTFA4J8xcO/kJ/1FcQ6x3Ag/5n6LZ6HRdL nuoL+K5pafefCQTxC1QL33da1Qq5erdXihob+pf/Fx3zgB0iOawHguow0 rbeEC5el80XtkeFgyLsaYEPSmfkvNKyLYnPYEcY6bAPYeINc5VbOWY5eJ GngVFnmPGF2bXT+2r2lsUgXDYWoj7J/4I2s3xNQtHgs6lrnw/RKWsPLga pJIPq0ubnlSI/mpF6mzuUoIkUTzvvtBqYjTrXqfVmpjGZBq5sh8Y+/JiL O3iUU1xuTA4NwVXbdGUvjcHbKU+y0NerOJAEOCXcZP3GwDF0Q8fCXCifV A==; X-IronPort-AV: E=McAfee;i="6400,9594,10411"; a="287363982" X-IronPort-AV: E=Sophos;i="5.92,281,1650956400"; d="scan'208";a="287363982" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jul 2022 06:18:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,281,1650956400"; d="scan'208";a="624725037" Received: from shwdeopenlab706.ccr.corp.intel.com ([10.239.183.102]) by orsmga008.jf.intel.com with ESMTP; 18 Jul 2022 06:18:50 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong Subject: [PATCH 09/10] CpuPageTableLib: Fix bug that wrongly requires extra size for mapping Date: Mon, 18 Jul 2022 21:18:30 +0800 Message-Id: <20220718131831.660-10-ray.ni@intel.com> X-Mailer: git-send-email 2.35.1.windows.2 In-Reply-To: <20220718131831.660-1-ray.ni@intel.com> References: <20220718131831.660-1-ray.ni@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable With following paging structure to map [2M-4K, 2M] as P =3D 1, RW =3D 0, [2M, 4M] as P =3D 1, RW =3D 1: PML4[0] -> PDPTE[0] -> PDE[0](RW =3D 0) -> PTE[255](P =3D 0, RW =3D 0) -> PDE[1](RW =3D 1) When a new request to map [2M-4K, 2M+4K] as P =3D 1, RW =3D 1, CpuPageTableMap() wrongly requests 4K buffer size for the new mapping request. But in fact, for [2M-4K, 2M] request, PTE[255] can be changed in place, for [2M, 2M+4K], no change is needed because PDE[1].RW =3D 1 already. The change fixes the bug. Signed-off-by: Ray Ni Signed-off-by: Zhiguang Liu Cc: Eric Dong --- .../Library/CpuPageTableLib/CpuPageTableMap.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 1205119fc8..16e6697ed4 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -272,6 +272,7 @@ PageTableLibMapInLevel ( IA32_MAP_ATTRIBUTE ChildAttribute;=0D IA32_MAP_ATTRIBUTE ChildMask;=0D IA32_MAP_ATTRIBUTE CurrentMask;=0D + IA32_MAP_ATTRIBUTE LocalParentAttribute;=0D =0D ASSERT (Level !=3D 0);=0D ASSERT ((Attribute !=3D NULL) && (Mask !=3D NULL));=0D @@ -284,6 +285,9 @@ PageTableLibMapInLevel ( NopAttribute.Bits.ReadWrite =3D 1;=0D NopAttribute.Bits.UserSupervisor =3D 1;=0D =0D + LocalParentAttribute.Uint64 =3D ParentAttribute->Uint64;=0D + ParentAttribute =3D &LocalParentAttribute;=0D +=0D //=0D // ParentPagingEntry ONLY is deferenced for checking Present and MustBeO= ne bits=0D // when Modify is FALSE.=0D @@ -420,7 +424,7 @@ PageTableLibMapInLevel ( }=0D =0D if (IsPle (&PagingEntry[Index], Level)) {=0D - PageTableLibSetPle (Level - 1, &PagingEntry[Index], 0, &ChildA= ttribute, &ChildMask);=0D + PageTableLibSetPle (Level, &PagingEntry[Index], 0, &ChildAttri= bute, &ChildMask);=0D } else {=0D PageTableLibSetPnle (&PagingEntry[Index].Pnle, &ChildAttribute= , &ChildMask);=0D }=0D @@ -664,13 +668,6 @@ PageTableMap ( //=0D // Update the page table when the supplied buffer is sufficient.=0D //=0D - ParentAttribute.Uint64 =3D 0;=0D - ParentAttribute.Bits.PageTableBaseAddress =3D 1;=0D - ParentAttribute.Bits.Present =3D 1;=0D - ParentAttribute.Bits.ReadWrite =3D 1;=0D - ParentAttribute.Bits.UserSupervisor =3D 1;=0D - ParentAttribute.Bits.Nx =3D 0;=0D -=0D Status =3D PageTableLibMapInLevel (=0D &TopPagingEntry,=0D &ParentAttribute,=0D --=20 2.35.1.windows.2