From: "Ni, Ray" <ray.ni@intel.com>
To: devel@edk2.groups.io
Cc: Zhiguang Liu <zhiguang.liu@intel.com>, Eric Dong <eric.dong@intel.com>
Subject: [PATCH 10/10] CpuPageTableLib: define IA32_PAGE_LEVEL enum type internally
Date: Mon, 18 Jul 2022 21:18:31 +0800 [thread overview]
Message-ID: <20220718131831.660-11-ray.ni@intel.com> (raw)
In-Reply-To: <20220718131831.660-1-ray.ni@intel.com>
The change doesn't change functionality behavior.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
---
UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h | 8 ++++++++
UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 12 ++++++------
2 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h
index 627f84e4e2..8d856d7c7e 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h
+++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h
@@ -20,6 +20,14 @@
#define REGION_LENGTH(l) LShiftU64 (1, (l) * 9 + 3)
+typedef enum {
+ Pte = 1,
+ Pde = 2,
+ Pdpte = 3,
+ Pml4 = 4,
+ Pml5 = 5
+} IA32_PAGE_LEVEL;
+
typedef struct {
UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
index 16e6697ed4..d3fdf13429 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
@@ -245,8 +245,8 @@ PageTableLibMapInLevel (
IN BOOLEAN Modify,
IN VOID *Buffer,
IN OUT INTN *BufferSize,
- IN UINTN Level,
- IN UINTN MaxLeafLevel,
+ IN IA32_PAGE_LEVEL Level,
+ IN IA32_PAGE_LEVEL MaxLeafLevel,
IN UINT64 LinearAddress,
IN UINT64 Length,
IN UINT64 Offset,
@@ -572,8 +572,8 @@ PageTableMap (
IA32_PAGING_ENTRY TopPagingEntry;
INTN RequiredSize;
UINT64 MaxLinearAddress;
- UINTN MaxLevel;
- UINTN MaxLeafLevel;
+ IA32_PAGE_LEVEL MaxLevel;
+ IA32_PAGE_LEVEL MaxLeafLevel;
IA32_MAP_ATTRIBUTE ParentAttribute;
if ((PagingMode == Paging32bit) || (PagingMode == PagingPae) || (PagingMode >= PagingModeMax)) {
@@ -606,8 +606,8 @@ PageTableMap (
return RETURN_INVALID_PARAMETER;
}
- MaxLeafLevel = (UINT8)PagingMode;
- MaxLevel = (UINT8)(PagingMode >> 8);
+ MaxLeafLevel = (IA32_PAGE_LEVEL)(UINT8)PagingMode;
+ MaxLevel = (IA32_PAGE_LEVEL)(UINT8)(PagingMode >> 8);
MaxLinearAddress = LShiftU64 (1, 12 + MaxLevel * 9);
if ((LinearAddress > MaxLinearAddress) || (Length > MaxLinearAddress - LinearAddress)) {
--
2.35.1.windows.2
next prev parent reply other threads:[~2022-07-18 13:18 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-18 13:18 [PATCH 00/10] UefiCpuPkg: Create CpuPageTableLib for manipulating X86 paging structs Ni, Ray
2022-07-18 13:18 ` [PATCH 01/10] " Ni, Ray
2022-07-18 13:49 ` [edk2-devel] " Gerd Hoffmann
2022-07-19 8:17 ` Ni, Ray
2022-08-15 16:23 ` Lendacky, Thomas
2022-08-16 2:25 ` Ni, Ray
2022-07-18 13:18 ` [PATCH 02/10] UefiCpuPkg/CpuPageTableLib: Return error on invalid parameters Ni, Ray
2022-07-18 13:18 ` [PATCH 03/10] CpuPageTableLib: Fix a bug when a bit is 1 in Attribute, 0 in Mask Ni, Ray
2022-07-18 13:18 ` [PATCH 04/10] CpuPageTableLib: Refactor the logic Ni, Ray
2022-07-18 13:18 ` [PATCH 05/10] CpuPageTableLib: Split the page entry when LA is aligned but PA is not Ni, Ray
2022-07-18 13:18 ` [PATCH 06/10] CpuPageTableLib: Avoid treating non-leaf entry as leaf one Ni, Ray
2022-07-18 13:18 ` [PATCH 07/10] CpuPageTableLib: Fix parent attributes are not inherited properly Ni, Ray
2022-07-18 13:18 ` [PATCH 08/10] CpuPageTableLib: Fix a bug to avoid unnecessary changing to page table Ni, Ray
2022-07-18 13:18 ` [PATCH 09/10] CpuPageTableLib: Fix bug that wrongly requires extra size for mapping Ni, Ray
2022-07-18 13:18 ` Ni, Ray [this message]
2022-08-09 3:46 ` [edk2-devel] [PATCH 00/10] UefiCpuPkg: Create CpuPageTableLib for manipulating X86 paging structs Dong, Eric
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