From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web08.27105.1658150328221476289 for ; Mon, 18 Jul 2022 06:18:53 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=kYp2EAe6; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: ray.ni@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658150333; x=1689686333; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iVKntT7IFrQuS1w953ZdWHJV+lSgMNNQ6mTAoVdeSPM=; b=kYp2EAe6/JFP7g7lyAOp+BalDcka4tUhdcIqwHWd7ZmquOeEQoMDsm/+ gDg6fyXRR9h00pasiEKPS89qtnaV0bzZp+2IMSwg60MZiVbtBeZBdcdq0 FxeNnVeJbFNIdvVeJ+H/FxoDuGCzbjf5yZ+IWaUFEPD8q4H51FP+BmOGF f6lJS9dG2f6Aga0d9UZ9Puu3e4SdfCgYrwx/zkW2QjSe6AMkJVkiESlf1 aV9thnrQk44T1ji8+dSET1Y/+Wgupf/3qgxnnM1WI5zOsgMP51iAGGfKZ BuRXOs+Vj45gAzV51HI33Bmwg3ebRCwot+YpQ/fsNNsJaiiWpVVJSyCP+ g==; X-IronPort-AV: E=McAfee;i="6400,9594,10411"; a="287364008" X-IronPort-AV: E=Sophos;i="5.92,281,1650956400"; d="scan'208";a="287364008" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jul 2022 06:18:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,281,1650956400"; d="scan'208";a="624725057" Received: from shwdeopenlab706.ccr.corp.intel.com ([10.239.183.102]) by orsmga008.jf.intel.com with ESMTP; 18 Jul 2022 06:18:51 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong Subject: [PATCH 10/10] CpuPageTableLib: define IA32_PAGE_LEVEL enum type internally Date: Mon, 18 Jul 2022 21:18:31 +0800 Message-Id: <20220718131831.660-11-ray.ni@intel.com> X-Mailer: git-send-email 2.35.1.windows.2 In-Reply-To: <20220718131831.660-1-ray.ni@intel.com> References: <20220718131831.660-1-ray.ni@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable The change doesn't change functionality behavior. Signed-off-by: Ray Ni Cc: Zhiguang Liu Cc: Eric Dong --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h | 8 ++++++++ UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 12 ++++++------ 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h b/UefiCpuPkg= /Library/CpuPageTableLib/CpuPageTable.h index 627f84e4e2..8d856d7c7e 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h @@ -20,6 +20,14 @@ =0D #define REGION_LENGTH(l) LShiftU64 (1, (l) * 9 + 3)=0D =0D +typedef enum {=0D + Pte =3D 1,=0D + Pde =3D 2,=0D + Pdpte =3D 3,=0D + Pml4 =3D 4,=0D + Pml5 =3D 5=0D +} IA32_PAGE_LEVEL;=0D +=0D typedef struct {=0D UINT64 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory=0D UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Write= =0D diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 16e6697ed4..d3fdf13429 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -245,8 +245,8 @@ PageTableLibMapInLevel ( IN BOOLEAN Modify,=0D IN VOID *Buffer,=0D IN OUT INTN *BufferSize,=0D - IN UINTN Level,=0D - IN UINTN MaxLeafLevel,=0D + IN IA32_PAGE_LEVEL Level,=0D + IN IA32_PAGE_LEVEL MaxLeafLevel,=0D IN UINT64 LinearAddress,=0D IN UINT64 Length,=0D IN UINT64 Offset,=0D @@ -572,8 +572,8 @@ PageTableMap ( IA32_PAGING_ENTRY TopPagingEntry;=0D INTN RequiredSize;=0D UINT64 MaxLinearAddress;=0D - UINTN MaxLevel;=0D - UINTN MaxLeafLevel;=0D + IA32_PAGE_LEVEL MaxLevel;=0D + IA32_PAGE_LEVEL MaxLeafLevel;=0D IA32_MAP_ATTRIBUTE ParentAttribute;=0D =0D if ((PagingMode =3D=3D Paging32bit) || (PagingMode =3D=3D PagingPae) || = (PagingMode >=3D PagingModeMax)) {=0D @@ -606,8 +606,8 @@ PageTableMap ( return RETURN_INVALID_PARAMETER;=0D }=0D =0D - MaxLeafLevel =3D (UINT8)PagingMode;=0D - MaxLevel =3D (UINT8)(PagingMode >> 8);=0D + MaxLeafLevel =3D (IA32_PAGE_LEVEL)(UINT8)PagingMode;=0D + MaxLevel =3D (IA32_PAGE_LEVEL)(UINT8)(PagingMode >> 8);=0D MaxLinearAddress =3D LShiftU64 (1, 12 + MaxLevel * 9);=0D =0D if ((LinearAddress > MaxLinearAddress) || (Length > MaxLinearAddress - L= inearAddress)) {=0D --=20 2.35.1.windows.2