From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web12.27079.1658150325580236005 for ; Mon, 18 Jul 2022 06:18:46 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=XyZ1LW/s; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: ray.ni@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658150326; x=1689686326; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2KpizpO3Fyf1jmW9hRA6Y4QG8FEfWID+mKN2SN35ikU=; b=XyZ1LW/srREVsGkismzw53W86k7sk7UPDPjD/0jxRUSOl8udRi8EOq7B nr1nxmzc6dsy6DFLMuWVDelPegoc9cbL10Y7/WWJfA2VbxJmom5YCA2Lk KL+hxb5AijGCx1sgaiVUpbwxEkr/SA6eucXgJu3TIBD5QDmIPOt78VpHq b4pci1jG+MP+u+hFXmLTRtp0gsZpKsaGwPxFXN3pn04gfgESdMi09sDvh kJbNgjPs3G1lMmm31Ub7dVDUQL3UrADVD0NKmT6r0IjJXqjI/CLwK+XiT 6d9CHg4uoRSzpRb99qXzbaxzT2aC7eTiEewbARFnUOT4htI0+gj7SRVA8 w==; X-IronPort-AV: E=McAfee;i="6400,9594,10411"; a="287363898" X-IronPort-AV: E=Sophos;i="5.92,281,1650956400"; d="scan'208";a="287363898" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jul 2022 06:18:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,281,1650956400"; d="scan'208";a="624724973" Received: from shwdeopenlab706.ccr.corp.intel.com ([10.239.183.102]) by orsmga008.jf.intel.com with ESMTP; 18 Jul 2022 06:18:43 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong Subject: [PATCH 04/10] CpuPageTableLib: Refactor the logic Date: Mon, 18 Jul 2022 21:18:25 +0800 Message-Id: <20220718131831.660-5-ray.ni@intel.com> X-Mailer: git-send-email 2.35.1.windows.2 In-Reply-To: <20220718131831.660-1-ray.ni@intel.com> References: <20220718131831.660-1-ray.ni@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable The patch replaces LinearAddress + Offset =3D=3D RegionStart with ((LinearAddress + Offset) & RegionMask) =3D=3D 0 The replace should not cause any behavior change. Because: 1. In first loop of while when LinearAddress + Offset =3D=3D RegionStart, because the lower "BitStart" bits of RegionStart are all-zero, all lower "BitStart" bits of (LinearAddress + Offset) are all-zero. Because all lower "BitStart" bits of RegionMask is all-one and bits are all-zero, ((LinearAddress + Offset) & RegionMask) =3D=3D 0. 2. In following loops of the while, even RegionStart is increased by RegionLength, the lower "BitStart" bits are still all-zero. So the two expressions still semantically equal to each other. Signed-off-by: Ray Ni Cc: Zhiguang Liu Cc: Eric Dong --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 429b014b7b..509fa5f7bd 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -360,7 +360,7 @@ PageTableLibMapInLevel ( PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_AD= DRESS (&ParentPagingEntry->Pnle);=0D while (Offset < Length && Index < 512) {=0D SubLength =3D MIN (Length - Offset, RegionStart + RegionLength - (Line= arAddress + Offset));=0D - if ((Level <=3D MaxLeafLevel) && (LinearAddress + Offset =3D=3D Region= Start) && (SubLength =3D=3D RegionLength)) {=0D + if ((Level <=3D MaxLeafLevel) && (((LinearAddress + Offset) & RegionMa= sk) =3D=3D 0) && (SubLength =3D=3D RegionLength)) {=0D //=0D // Create one entry mapping the entire region (1G, 2M or 4K).=0D //=0D --=20 2.35.1.windows.2