[PATCH 05/10] CpuPageTableLib: Split the page entry when LA is aligned but PA is not

["Ni, Ray" <ray.ni@intel.com>]

When PageTableMap() is called to create non 1:1 mapping
such as [0, 1G) to [8K, 1G+8K), it should split the page entry to the
4K page level, but old logic has a bug that it just uses 1G page
entry.

The patch fixes the bug.

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
---
 UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
index 509fa5f7bd..dc37ca3647 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
@@ -360,7 +360,12 @@ PageTableLibMapInLevel (
   PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&ParentPagingEntry->Pnle);
   while (Offset < Length && Index < 512) {
     SubLength = MIN (Length - Offset, RegionStart + RegionLength - (LinearAddress + Offset));
-    if ((Level <= MaxLeafLevel) && (((LinearAddress + Offset) & RegionMask) == 0) && (SubLength == RegionLength)) {
+    if ((Level <= MaxLeafLevel) &&
+        (((LinearAddress + Offset) & RegionMask) == 0) &&
+        (((IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute) + Offset) & RegionMask) == 0) &&
+        (SubLength == RegionLength)
+        )
+    {
       //
       // Create one entry mapping the entire region (1G, 2M or 4K).
       //
-- 
2.35.1.windows.2