From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web12.27079.1658150325580236005 for ; Mon, 18 Jul 2022 06:18:46 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=YtsEWFwx; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: ray.ni@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658150326; x=1689686326; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NYNnW/sRiJTtlMQW7YfUhfgJjBc4wgTBrRUSLWykPYs=; b=YtsEWFwxxoapSZSD9FBKhfMVW/nuHY8o0Pck6fjldUQOVXEez263a76l Djclf5Yc1gqS4TbmaeRjHww3QGJYakqrawy1s1rwDmC9bNA/EFwQMVbZN 3Gn4YuPtixwaP8uGA30sQI1y4Yzhy3jPAZASSQxwoXG7eGtz7v0NFc9fS 8eV//g4wfETfhPxgZSEjpY3HDVRrTm4+Af7S2gqsAJWuix+zrfhf+Y5wi MLuog6T+ROka1KD2iO/TyOLKScLZONa9OmW+EH23icLj33IaqXf98Q7Tz N1YKoYU2oPtI9SehRujfr5lBAzpJwM/bOVOvjJafHfanuIwuEYyA7tz8/ Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10411"; a="287363901" X-IronPort-AV: E=Sophos;i="5.92,281,1650956400"; d="scan'208";a="287363901" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jul 2022 06:18:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,281,1650956400"; d="scan'208";a="624724978" Received: from shwdeopenlab706.ccr.corp.intel.com ([10.239.183.102]) by orsmga008.jf.intel.com with ESMTP; 18 Jul 2022 06:18:44 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong Subject: [PATCH 05/10] CpuPageTableLib: Split the page entry when LA is aligned but PA is not Date: Mon, 18 Jul 2022 21:18:26 +0800 Message-Id: <20220718131831.660-6-ray.ni@intel.com> X-Mailer: git-send-email 2.35.1.windows.2 In-Reply-To: <20220718131831.660-1-ray.ni@intel.com> References: <20220718131831.660-1-ray.ni@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable When PageTableMap() is called to create non 1:1 mapping such as [0, 1G) to [8K, 1G+8K), it should split the page entry to the 4K page level, but old logic has a bug that it just uses 1G page entry. The patch fixes the bug. Signed-off-by: Zhiguang Liu Cc: Ray Ni Cc: Eric Dong --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 509fa5f7bd..dc37ca3647 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -360,7 +360,12 @@ PageTableLibMapInLevel ( PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_AD= DRESS (&ParentPagingEntry->Pnle);=0D while (Offset < Length && Index < 512) {=0D SubLength =3D MIN (Length - Offset, RegionStart + RegionLength - (Line= arAddress + Offset));=0D - if ((Level <=3D MaxLeafLevel) && (((LinearAddress + Offset) & RegionMa= sk) =3D=3D 0) && (SubLength =3D=3D RegionLength)) {=0D + if ((Level <=3D MaxLeafLevel) &&=0D + (((LinearAddress + Offset) & RegionMask) =3D=3D 0) &&=0D + (((IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute) + Offset= ) & RegionMask) =3D=3D 0) &&=0D + (SubLength =3D=3D RegionLength)=0D + )=0D + {=0D //=0D // Create one entry mapping the entire region (1G, 2M or 4K).=0D //=0D --=20 2.35.1.windows.2