From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-qt1-f181.google.com (mail-qt1-f181.google.com [209.85.160.181]) by mx.groups.io with SMTP id smtpd.web08.1595.1658535729136005758 for ; Fri, 22 Jul 2022 17:22:09 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@gmail.com header.s=20210112 header.b=eoQDO9/g; spf=pass (domain: gmail.com, ip: 209.85.160.181, mailfrom: benjamin.doron00@gmail.com) Received: by mail-qt1-f181.google.com with SMTP id g24so4656210qtu.2 for ; Fri, 22 Jul 2022 17:22:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1BjNdOacbbpkc4TTDEZsPGqjgV9oYbh88ZpPkAvaO/A=; b=eoQDO9/gN9xmjEQgoPgjQgsIzbjWtDlZFq7NWPsECnoYeOQvQegXYQCRKd00KnC7v+ z1U259x+JMaapxsYuTforlKW1tOFqneYFfKNp7AfXr7soxpX+OroGhSe+Y/2QJtmvEvJ ceZaBdKkOFJlaFEvidgSiVHaTD5Y5LU6nl4yKK+zCs9Xk3B+gq+21vqcUM2+2P7/CYuE zx6YbSTg2cG/u0h/+VPGoRUeXr+djRxZYK/lQRuUDstWnneZHWJv6ykzr5xEAWpfdsZg 6sWXU8lf9TwP5R/b26N9IoSxy/y+3qSYntuHMfrjDmipYB2wllEWfjJt+TEc+odEqsWJ VxaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1BjNdOacbbpkc4TTDEZsPGqjgV9oYbh88ZpPkAvaO/A=; b=Z3rZxOh4Izp/4YFkf8RFtgeMruuXWyc4OOpBAjJfH6tHsIAZ7e1goDIckCdsSt6qEA bmzlYZJ8Y5vVqMJC+rt4MQPum2sIEqkaGsXaqAuCnGG0XDZnfiBufZKhfwAQKyjolnOu TEs1fsozXLRSJDZtL5cMWjW0is7Lop2Evz06ePQJWuGl6FXequU/MR2Su7FjkV6bSl5j 7kmPgRVuJwsfvWoaAqNJK7gMrwopTqJN/qpRz3esz9RtZKOghKhBIzxGGU+Z4a+Hf2or lfdXMQi5UcH8QIgDNl85K6ZsM6ZOAQwygQbdzl/yxYCFwOZLnDIedRL0TmqI53vuJN+A ukiA== X-Gm-Message-State: AJIora+ctL6sPvvvkK+xXbsxKPCr2GrpPZUmfvOIXwCCGKRLjyKYN3M9 JVNmnhQ9Tx67Iw/rYjGgzWHZ2dN1O+E= X-Google-Smtp-Source: AGRyM1vc9YD6EoFbZSKwQQzWSQKqKXd2uEhacNSdYjEQS4/gHiuk4gxMUuK9/jp0eUGOvHUiOH0S2g== X-Received: by 2002:ac8:7d8a:0:b0:31f:dcc:8e3d with SMTP id c10-20020ac87d8a000000b0031f0dcc8e3dmr2326492qtd.500.1658535727961; Fri, 22 Jul 2022 17:22:07 -0700 (PDT) Return-Path: Received: from aturtleortwo-benjamindomain.. ([2607:f2c0:e98c:e:39b7:8453:91b5:69bf]) by smtp.gmail.com with ESMTPSA id z8-20020ac84308000000b0031ee1f0c420sm3766705qtm.10.2022.07.22.17.22.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Jul 2022 17:22:07 -0700 (PDT) From: "Benjamin Doron" To: devel@edk2.groups.io Cc: Nate DeSimone , Ankit Sinha , Sai Chaganty , Isaac Oram , Liming Gao Subject: [PATCH v1 3/5] S3FeaturePkg: Implement S3 resume Date: Fri, 22 Jul 2022 20:19:59 -0400 Message-Id: <20220723002001.1309418-4-benjamin.doron00@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220723002001.1309418-1-benjamin.doron00@gmail.com> References: <20220723002001.1309418-1-benjamin.doron00@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Follow-up commits to MinPlatform (AcpiPlatform and PeiFspWrapperHobProcessLib for memory) and FSP-related board libraries required for successful S3 resume. Cc: Nate DeSimone Cc: Ankit Sinha Cc: Sai Chaganty Cc: Isaac Oram Cc: Liming Gao Signed-off-by: Benjamin Doron --- Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf | 14 ++= ++ Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf | 8 +- Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc | 56 ++= ++++++++++- Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c | 83 ++= ++++++++++++++++-- Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf | 8 +- 5 files changed, 161 insertions(+), 8 deletions(-) diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory= .fdf b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf index 9e17f853c630..44aa2fb1b85e 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf +++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf @@ -2,7 +2,21 @@ # FDF file for post-memory S3 advanced feature modules.=0D #=0D # Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D +# Copyright (c) 2022, Baruch Binyamin Doron.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D ##=0D +=0D +## Dependencies=0D + INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf=0D + INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf=0D + # FSP may perform CPU finalisation, requires CpuInitDxe from closed code= =0D + # - Presently, PiSmmCpuDxeSmm shall perform finalisation with this data= =0D + INF UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf=0D +=0D +## Save-state module stack=0D + INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf=0D +=0D +## Restore-state module stack=0D + INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutor= Dxe.inf=0D diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.= fdf b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf index fdd16a4e0356..e130fa5f098d 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf +++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf @@ -2,9 +2,15 @@ # FDF file for pre-memory S3 advanced feature modules.=0D #=0D # Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D +# Copyright (c) 2022, Baruch Binyamin Doron.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D ##=0D =0D -INF S3FeaturePkg/S3Pei/S3Pei.inf=0D +## Dependencies=0D + INF S3FeaturePkg/S3Pei/S3Pei.inf=0D + INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf=0D +=0D +## Restore-state module stack=0D + INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf=0D diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.= dsc b/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc index cc34e785076a..77dc7f9da61c 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc +++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc @@ -7,6 +7,7 @@ # for the build infrastructure.=0D #=0D # Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
=0D +# Copyright (c) 2022, Baruch Binyamin Doron.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -25,6 +26,10 @@ !error "DXE_ARCH must be specified to build this feature!"=0D !endif=0D =0D +[PcdsFixedAtBuild]=0D + # Attempts to improve performance at the cost of more DRAM usage=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE=0D +=0D ##########################################################################= ######=0D #=0D # Library Class section - list of all Library Classes needed by this featu= re.=0D @@ -32,7 +37,15 @@ ##########################################################################= ######=0D =0D [LibraryClasses.common.PEIM]=0D - SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/P= eiSmmAccessLib.inf=0D + # TODO: Some platforms (TGL) do a no-op.=0D + SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSm= ramc/PeiSmmAccessLib.inf=0D + SmmControlLib|IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLi= b/PeiSmmControlLib.inf=0D +=0D +[LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.DXE_SMM_DRIVER]=0D + #######################################=0D + # Edk2 Packages=0D + #######################################=0D + S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScrip= tLib.inf=0D =0D ##########################################################################= ######=0D #=0D @@ -65,3 +78,44 @@ =0D # Add components here that should be included in the package build.=0D S3FeaturePkg/S3Pei/S3Pei.inf=0D + UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf=0D + UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf=0D +=0D +#=0D +# Feature DXE Components=0D +#=0D +=0D +# @todo: Change below line to [Components.$(DXE_ARCH)] after https://bugzi= lla.tianocore.org/show_bug.cgi?id=3D2308=0D +# is completed.=0D +[Components.X64]=0D + #####################################=0D + # S3 Feature Package=0D + #####################################=0D +=0D + # Add library instances here that are not included in package components= and should be tested=0D + # in the package build.=0D +=0D + # Add components here that should be included in the package build.=0D + UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf=0D + MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf=0D + UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf=0D + MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf=0D + # NOTE: DebugLibReportStatusCode will be after exit-BS=0D + # - DebugLibSerialPort requires care to avoid gBS in SerialPortInitializ= e()=0D + # - No variable assigns after ReadyToLock take effect, due to LockBox co= py=0D + MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.= inf=0D +=0D +##########################################################################= #########################=0D +#=0D +# BuildOptions Section - Define the module specific tool chain flags that = should be used as=0D +# the default flags for a module. These flags are a= ppended to any=0D +# standard flags that are defined by the build proc= ess. They can be=0D +# applied for any modules or only those modules wit= h the specific=0D +# module style (EDK or EDKII) specified in [Compone= nts] section.=0D +#=0D +# For advanced features, it is recommended to enabl= e [BuildOptions] in=0D +# the applicable INF file so it does not affect the= whole board package=0D +# build when this DSC file is active.=0D +#=0D +##########################################################################= #########################=0D +[BuildOptions]=0D diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c b/Fe= atures/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c index b0aaa04962c8..6acb894b6fc9 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c @@ -2,12 +2,87 @@ Source code file for S3 PEI module=0D =0D Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D +Copyright (c) 2022, Baruch Binyamin Doron.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D =0D +#include =0D +#include =0D +#include =0D #include =0D #include =0D +#include =0D +=0D +// TODO: Finalise implementation factoring=0D +#define R_SA_PAM0 (0x80)=0D +#define R_SA_PAM5 (0x85)=0D +#define R_SA_PAM6 (0x86)=0D +=0D +/**=0D + This function is called after FspSiliconInitDone installed PPI.=0D + For FSP API mode, this is when FSP-M HOBs are installed into EDK2.=0D +=0D + @param[in] PeiServices Pointer to PEI Services Table.=0D + @param[in] NotifyDesc Pointer to the descriptor for the Notification= event that=0D + caused this function to execute.=0D + @param[in] Ppi Pointer to the PPI data associated with this f= unction.=0D +=0D + @retval EFI_STATUS Always return EFI_SUCCESS=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +FspSiliconInitDoneNotify (=0D + IN EFI_PEI_SERVICES **PeiServices,=0D + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc,=0D + IN VOID *Ppi=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_BOOT_MODE BootMode;=0D + UINT64 MchBaseAddress;=0D +=0D + Status =3D PeiServicesGetBootMode (&BootMode);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + // Enable PAM regions for AP wakeup vector (resume)=0D + // - CPU is finalised by PiSmmCpuDxeSmm, not FSP. So, it's safe here?=0D + // TODO/TEST: coreboot does this unconditionally, vendor FWs may not (te= st resume). Should we?=0D + // - It is certainly interesting that only PAM0, PAM5 and PAM6 are defin= ed for KabylakeSiliconPkg.=0D + // - Also note that 0xA0000-0xFFFFF is marked "reserved" in FSP HOB - th= is does not mean=0D + // that the memory is unusable, perhaps this is precisely because it w= ill contain=0D + // the AP wakeup vector.=0D + if (BootMode =3D=3D BOOT_ON_S3_RESUME) {=0D + MchBaseAddress =3D PCI_LIB_ADDRESS (0, 0, 0, 0);=0D + PciWrite8 (MchBaseAddress + R_SA_PAM0, 0x30);=0D + PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 1), 0x33);=0D + PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 2), 0x33);=0D + PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 3), 0x33);=0D + PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 4), 0x33);=0D + PciWrite8 (MchBaseAddress + R_SA_PAM5, 0x33);=0D + PciWrite8 (MchBaseAddress + R_SA_PAM6, 0x33);=0D + }=0D +=0D + //=0D + // Install EFI_PEI_MM_ACCESS_PPI for S3 resume case=0D + //=0D + Status =3D PeiInstallSmmAccessPpi ();=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + //=0D + // Install EFI_PEI_MM_CONTROL_PPI for S3 resume case=0D + //=0D + Status =3D PeiInstallSmmControlPpi ();=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + return Status;=0D +}=0D +=0D +EFI_PEI_NOTIFY_DESCRIPTOR mFspSiliconInitDoneNotifyDesc =3D {=0D + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINA= TE_LIST),=0D + &gFspSiliconInitDonePpiGuid,=0D + FspSiliconInitDoneNotify=0D +};=0D =0D /**=0D S3 PEI module entry point=0D @@ -25,12 +100,10 @@ S3PeiEntryPoint ( IN CONST EFI_PEI_SERVICES **PeiServices=0D )=0D {=0D - EFI_STATUS Status;=0D + EFI_STATUS Status;=0D =0D - //=0D - // Install EFI_PEI_MM_ACCESS_PPI for S3 resume case=0D - //=0D - Status =3D PeiInstallSmmAccessPpi ();=0D + Status =3D PeiServicesNotifyPpi (&mFspSiliconInitDoneNotifyDesc);=0D + ASSERT_EFI_ERROR (Status);=0D =0D return Status;=0D }=0D diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf b/= Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf index e485eac9521f..173919bb881e 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf @@ -18,10 +18,13 @@ [LibraryClasses]=0D PeimEntryPoint=0D PeiServicesLib=0D + DebugLib=0D SmmAccessLib=0D + SmmControlLib=0D =0D [Packages]=0D MdePkg/MdePkg.dec=0D + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec=0D IntelSiliconPkg/IntelSiliconPkg.dec=0D S3FeaturePkg/S3FeaturePkg.dec=0D =0D @@ -31,5 +34,8 @@ [FeaturePcd]=0D gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable=0D =0D +[Ppis]=0D + gFspSiliconInitDonePpiGuid=0D +=0D [Depex]=0D - gEfiPeiMemoryDiscoveredPpiGuid=0D + TRUE=0D --=20 2.36.1